pcengines · miczyg1 · Jan 26, 2021 · Jan 18, 2021 · Jan 15, 2021 · Jan 6, 2021
diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs
diff --git a/3rdparty/blobs b/3rdparty/blobs
diff --git a/3rdparty/fsp b/3rdparty/fsp
diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode
diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -13,6 +13,10 @@ Please use [pce-fw-builder](https://github.com/pcengines/pce-fw-builder)
 
 ## [Unreleased]
 
+## [v4.13.0.3] - 2021-01-27
+### Changed
+- rebased with official coreboot repository commit 5e6e5c1
+
 ## [v4.13.0.2] - 2020-12-28
 ### Changed
 - rebased with official coreboot repository commit 8edb48b
@@ -480,7 +484,8 @@ redundant code which was similar for APU2/3/5 boards.
 - turn off D4 and D5 leds on boot
 - enable power on after power failure
 
-[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.13.0.2...develop
+[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.13.0.3...develop
+[v4.13.0.3]: https://github.com/pcengines/coreboot/compare/v4.13.0.2...v4.13.0.3
 [v4.13.0.2]: https://github.com/pcengines/coreboot/compare/v4.13.0.1...v4.13.0.2
 [v4.13.0.1]: https://github.com/pcengines/coreboot/compare/v4.12.0.6...v4.13.0.1
 [v4.12.0.6]: https://github.com/pcengines/coreboot/compare/v4.12.0.5...v4.12.0.6

diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md
@@ -65,3 +65,33 @@ The reference implementation is
 * Test how well CAR works with x86_64 and paging
 * Improve mode switches
 * Test libgfxinit / VGA Option ROMs / FSP
+
+## Known bugs on real hardware
+
+According to Intel x86_64 mode hasn't been validated in CAR environments.
+Until now it could be verified on various Intel platforms and no issues have
+been found.
+
+## Known bugs on KVM enabled qemu
+
+The `x86_64` reference code runs fine in qemu soft-cpu, but has serious issues
+when using KVM mode on some machines. The workaround is to *not* place
+page-tables in ROM, as done in
+[CB:49228](https://review.coreboot.org/c/coreboot/+/49228).
+
+Here's a list of known issues:
+
+* After entering long mode, the FPU doesn't work anymore, including accessing
+  MMX registers. It works fine before entering long mode. It works fine when
+  switching back to protected mode. Other registers, like SSE registers, are
+  working fine.
+* Reading from virtual memory, when the page tables are stored in ROM, causes
+  the MMU to abort the "page table walking" mechanism when the lower address
+  bits of the virtual address to be translated have a specific pattern.
+  Instead of loading the correct physical page, the one containing the
+  page tables in ROM will be loaded and used, which breaks code and data as
+  the page table doesn't contain the expected data. This in turn leads to
+  undefined behaviour whenever the 'wrong' address is being read.
+* Disabling paging in compability mode crashes the CPU.
+* Returning from long mode to compability mode crashes the CPU.
+* Entering long mode crashes on AMD host platforms.
diff --git a/Documentation/drivers/index.md b/Documentation/drivers/index.md
@@ -4,7 +4,9 @@ The drivers can be found in `src/drivers`. They are intended for onboard
 and plugin devices, significantly reducing integration complexity and
 they allow to easily reuse existing code accross platforms.
 
+* [Intel DPTF](dptf.md)
 * [IPMI KCS](ipmi_kcs.md)
 * [SMMSTORE](smmstore.md)
 * [SoundWire](soundwire.md)
 * [SMMSTOREv2](smmstorev2.md)
+* [USB4 Retimer](retimer.md)
diff --git a/Documentation/getting_started/gpio.md b/Documentation/getting_started/gpio.md
@@ -129,3 +129,13 @@ If no pullup or pulldown is declared with these, they may end up "floating",
 i.e., not at logical high or logical low. This can cause problems such as
 unwanted power consumption or not reading the pin correctly, if it was intended
 to be strapped.
+
+## Pad-related known issues and workarounds
+
+### LPC_CLKRUNB blocks S0ix states when board uses eSPI
+
+When using eSPI, the pad implementing `LPC_CLKRUNB` must be set to GPIO mode.
+Other pin settings i.e. Rx path enable/disable, Tx path enable/disable, pull up
+enable/disable etc are ignored. Leaving this pin in native mode will keep the
+LPC Controller awake and prevent S0ix entry. This issues is know at least on
+Apollolake and Geminilake.
diff --git a/Documentation/index.md b/Documentation/index.md
@@ -187,5 +187,6 @@ Contents:
 * [SuperIO](superio/index.md)
 * [Vendorcode](vendorcode/index.md)
 * [Utilities](util.md)
+* [coreboot infrastructure](infrastructure/index.md)
 * [Release notes for past releases](releases/index.md)
 * [Flashing firmware tutorial](flash_tutorial/index.md)