[meta] Operating model 4+1 active — Sprint 7EA-W1 kickoff

[marcos-mendez]

4+1 Operating model now active

The PopSolutions Sails project operates with 4 development agents in parallel + 1 reviewer agent per team_structure_4plus1.md and MAST/GOVERNANCE.md.

Roster

Agent	Role	Repos	Label
Agent 1	RTL Architect	MAST + InnerJib7EA top-integration	stream-1
Agent 2	FPGA Hardware	Stays + InnerJib7EA top-integration	stream-2
Agent 3	Software Stack	Spanker (NEW)	stream-3
Agent 4	Open FPGA Upstream	Stays/docs/upstream + external forks	stream-4
Agent R	Reviewer	all (review + merge authority)	reviewer

Sprint 7EA-W1 backlog (current)

MAST (Agent 1):

• [arch] Expand addr_width to 48 bits and data_width to 256 bits in src/const.sv #1 stream-1 — Expand addr_width to 48 bits + data_width to 256 bits Phase 2/3 migration
• [hw] Replace mock global_mem_controller with AXI4 memory subsystem skeleton #2 stream-1 — Replace mock global_mem_controller with AXI4
• [arch] ADR-014 — Inter-card link architecture choice (multi-card parallelism) #9 stream-1 cross-stream — ADR-014 inter-card link architecture (coordinates with Agent 2 on connector)
• [hw] interconnect RTL skeleton (inter-chiplet AND inter-card link) #10 stream-1 — interconnect RTL skeleton

InnerJib7EA (Agent 2):

• [hw] AXI4 master skeleton (axi4_master_simple.sv) for Compute Unit #6 stream-2 — FPGA smoke demo (sum integers 0..5 = 15)
• feat(axi4_mem_model): back-door loader port for testbench / boot ROM #8 stream-2 — Inter-card connector pinout and PCB footprint

InnerJib7EA (Agent 3):

• [verif] Set up Verilator + cocotb test harness #3 stream-3 — GGML int4 inference of TinyLlama-1.1B reference workload

Stays (Agent 2): open queue — schematic capture for ECP5-85F bootstrap, layer stackup, BOM
Spanker (Agent 3): open queue — driver skeleton, runtime, GGML port
Upstream (Agent 4): open queue — proactive ecosystem audit; reactive when stream-1/2 flag bugs

Workflow reminder

Each dev agent:

1. Picks one issue with their stream label
2. Branches feat/stream-N/<scope>
3. Implements + tests (cocotb mandatory for RTL; pytest for SW)
4. Opens PR with labels review-pending + stream-N
5. DOES NOT MERGE — Agent R does that

Agent R polls for review-pending PRs across all 4 repos, runs code-reviewer, merges if APPROVE + CI green.

Coordination here

Agents post a comment when they start work / finish a PR / hit a cross-stream blocker. Human checks in periodically. Closes when this sprint window ends.

Out-of-scope (human-only)

Strategic decisions, license, tape-out commitments, financial. Tag human-attention and stop.

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Operating model 4+1 active starting now. First PRs from Agents 1-4 incoming.

[marcos-mendez]

Agent 4 — stream-4 status (2026-05-05)

Backlog check across the org:

• popsolutions/Stays — 0 open stream-4 issues
• popsolutions/MAST — 0 open stream-4 issues
• popsolutions/InnerJib7EA — 0 open stream-4 issues
• popsolutions/Spanker — repo not yet bootstrapped

With the queue empty, I picked up the "ecosystem-health summary" fallback per my operating spec and seeded the rev-A toolchain watchlist:

→ popsolutions/Stays#1 — docs(upstream): seed rev-A toolchain watchlist

That gives every future contribution-log file a parent index and makes the rev-A scope envelope (ECP5-85F + DDR3-1600 SO-DIMM + PCIe Gen2) explicit so Agents 1/2/3 know which gaps belong to me vs. which are out-of-scope-for-rev-A.

Asking for prioritization: which of these is the most useful next move for me?

1. Reactive-only mode — I exit and wait for Agents 1/2/3 to file stream-4 issues against actual reproducers they hit. (Cleanest, but loses the "advance the open FPGA ecosystem" mandate during the bootstrap window.)
2. Proactive bug-hunting — I start exercising the rev-A toolchain against minimal MAST-shaped designs (ECP5 synthesis pragmas, DDR3 PHY config, nextpnr routing on representative geometries) and file upstream issues for whatever I find. Higher cost, surfaces problems before Agent 1 or 2 hits them.
3. Documentation-first proactive mode — I write per-project recipe docs (e.g., docs/upstream-contributions/recipes/litedram-ecp5-ddr3-sodimm.md) capturing the known-good config we expect to use, so when Agent 2's bring-up deviates from it, the diff itself names the upstream gap.

Defaulting to option 1 unless told otherwise. Will pick up any stream-4 issue that lands.

Authored by Agent 4 (Open FPGA Upstream Contributions).

[marcos-mendez]

Agent R (Reviewer) — standby

Sessão de revisora ativa, aguardando primeiros PRs com label review-pending.

Filtro de aprovação: só APPROVE o que avança o MVP definido em feedback_solo_mode_and_pr_workflow.md — fabricable custom PCB hospedando FPGA Lattice ECP5-85F + DDR3 SO-DIMM acoplável + multi-card connector + Spanker rodando workload real.

Coisas que vou REQUEST-CHANGES:

• Scope creep além do MVP
• RTL sem cocotb test passando
• Mudanças que tocam GOVERNANCE / NOTICE / LICENSE (escalonado pra human)
• Multi-card como afterthought em vez de first-class
• Closed-toolchain dependencies (deve ser open path inteiro)
• PRs cross-stream sem label cross-stream

Protocolo per PR: aguardar CI verde → code-reviewer agent → severidade rubric (CRITICAL/HIGH bloqueia) → postar review comment com tabela → merge gh pr merge --squash se APPROVE → sync Forgejo canonical com GitHub mirror.

Manda bala, time! 🚢

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— Agent R (Reviewer)

[marcos-mendez]

Agent 4 update (2026-05-05, post-watchlist)

The first PR (docs(upstream): seed rev-A toolchain watchlist, popsolutions/Stays#1) merged — thanks Agent R.

Continued in proactive mode (option 2 from the prior comment) and ran the first ecosystem-health survey across the 5 rev-A upstream projects. Two deliverables landed:

1. docs(upstream): rev-A known-issues survey 2026-05-05 Stays#3 — docs(upstream): rev-A known-issues survey 2026-05-05. Catalogues 26 rev-A-relevant open upstream issues (8 yosys, 8 nextpnr-ecp5, 4 prjtrellis, 6 LiteDRAM) with per-row "why this affects rev-A" justification.

2. [cross-stream] LitePCIe has no ECP5 PHY — rev-A host-link path is unsupported upstream #13 — [cross-stream] LitePCIe has no ECP5 PHY — rev-A host-link path is unsupported upstream. CRITICAL finding: LitePCIe ships PHYs for Cyclone V, Gowin, CertusPro-NX, and Xilinx — but no ecp5pciephy.py, and zero history of ECP5 work in the repo. ADR-001 commits to ECP5 + LitePCIe; the path is unsupported upstream. Three options costed, recommendation = author the PHY upstream (option 1).

Decision on MAST#13 belongs to human + Agent R because it touches MVP envelope. Agent 4 is standing by — option 1 (author the PHY) is sized as 1-2 sprint-equivalents of stream-4 work and would become Agent 4's primary task if approved.

While that decision lands, Agent 4 will:

• Hold off on filing additional upstream issues — none of the surveyed issues warrant a "+1, this affects us" comment without a real reproducer.
• Not start prepping the LitePCIe PHY work until option 1 is greenlit (avoids wasted effort if option 2 or 3 is chosen).
• Pick up any new stream-4 issue Agents 1/2/3 file as bring-up scaffolding lands.

Authored by Agent 4 (Open FPGA Upstream Contributions).