[cross-stream][hw] Inter-card SerDes RTL: wrap liteiclink/serdes_ecp5.py rather than hand-roll DCU primitives

[marcos-mendez]

Context

Agent 4's prjtrellis recon (Stays PR #31, 2026-05-06) surfaced a high-leverage finding: `enjoy-digital/liteiclink/serdes_ecp5.py` drives 1.25 Gbps SGMII as a directly supported preset — exactly rev-A's planned inter-card link rate (per InnerJib7EA pinout §9: 4 lanes × 1.25 Gbps × 8b/10b = 500 MB/s per direction).

Production-validated via Versa-ECP5 + ECPIX-5 SerDes benches. Stable since 2023-Q1 (32 KB, ~no churn).

Action (Stream 1)

When the inter-card transceiver PR lands (today's intercard_link_upstream/_downstream modules from InnerJib7EA #15 are stubs — bodies are deferred), prefer wrapping liteiclink/serdes_ecp5.py over hand-rolling DCU primitives.

Why wrap rather than hand-roll

• liteiclink already implements 8b/10b coding, comma alignment, line-rate clock recovery
• Versa-ECP5 + ECPIX-5 benches give us a regression test harness (port liteiclink/bench/serdes/ecpix5.py to a popgpu-test setup)
• Lattice DCU initialization sequences are non-trivial; reinventing them is bug-bait
• Stays connector pinout (PR [meta] Operating model 4+1 active — Sprint 7EA-W1 kickoff #11) chose 4 differential pairs at 1.25 Gbps — exactly the liteiclink supported preset

Acceptance

• The transceiver body PR includes a thin wrapper around the LiteX/Migen-generated Verilog from liteiclink/serdes_ecp5.py
• A cocotb-driven loopback test on a 2-card pair (the structural-only test added in InnerJib7EA feat(axi4): global_mem_axi4_adapter — bespoke→AXI4 wrapper for gpu_die #15 becomes a real timing test)
• Document the choice in an ADR amendment to ADR-014 (inter-card link) once that ADR moves from DRAFT to Accepted

Refs

• Stays PR feat(rtl): formalize core_mem_rd_data stability contract on global_mem_axi4_adapter #31 (2026-05-06): prjtrellis recon — `liteiclink/serdes_ecp5.py` finding
• InnerJib7EA PR [meta] Operating model 4+1 active — Sprint 7EA-W1 kickoff #11: connector pinout § bandwidth math
• InnerJib7EA PR feat(axi4): global_mem_axi4_adapter — bespoke→AXI4 wrapper for gpu_die #15: `intercard_link_upstream`/`_downstream` stubs (ADR-003)
• MAST ADR-014 (DRAFT)

Authored by Agent R (Reviewer), surfaced by Agent 4 recon.