Feature Support

The tool can parse all of the SystemVerilog language but will only accept some language features in modules chosen for synthesis. The table below lists select sections of the 2017 version of the SystemVerilog Language Reference Manual (IEEE 1800-2017) and reports the status of synthesis support for individual language features.

The Language Reference Manual defines syntax and simulation semantics. It does not define which parts of the language are synthesizable, nor does it define the expected deviation of synthesis semantics from simulation semantics. On these questions yosys-slang does not follow a formal specification but aims for compatibility with industrial synthesis tools.

Features listed as unsupported or partially supported are considered synthesizable and in scope for future yosys-slang development. The table is under construction. Feel free to contribute by filling missing data or refining existing entries.

Section	Status	Note
3. Design and verification building blocks
3.3 Modules	supported
3.4 Programs	non-synthesizable
3.5 Interfaces	supported	TODO: link to hierarchy page with limitations
3.6 Checkers	no data
3.7 Primitives		See sections 28 and 29
3.8 Subroutines	supported
3.9 Packages	supported
3.10 Configurations	supported
6. Data types
6.6 Net types	partial support	Net types tri0 tri1 trireg supply0 supply1 unsupported interconnect unsupported
6.7 Net declarations	supported
6.8 Variable declarations	supported
6.9 Vector declarations	supported
6.10 Implicit declarations	supported
6.11 Integer data types	supported
6.12 Real, shortreal, and realtime data types	non-synthesizable	Supported in constant functions. See #282 tracking support in parameters and attributes
6.13 Void data type	supported
6.14 Chandle data type	non-synthesizable
6.15 Class	no data
6.16 String data type	non-synthesizable	Supported in constant functions
6.17 Event data type	non-synthesizable
6.18 User-defined types	supported
6.19 Enumerations	partial support
6.20 Constants	partial support	References to const unsupported, see #93
6.21 Scope and lifetime	supported
6.22 Type compatibility	supported
6.23 Type operator	supported
6.24 Casting	supported	$cast non-synthesizable
6.25 Parameterized data types	supported
7. Aggregate data types
7.2 Structures	supported
7.3 Unions	unsupported
7.4 Packed and unpacked arrays	supported
7.5 Dynamic arrays	non-synthesizable	Supported in constant functions
7.6 Array assignments	supported
7.7 Arrays as arguments to subroutines	supported
7.8 Associative arrays	non-synthesizable	Supported in constant functions
7.9 Associative array methods	non-synthesizable	Supported in constant functions
7.10 Queues	non-synthesizable	Supported in constant functions
7.11 Array querying functions	unsupported	Supported in constant functions
7.12 Array manipulation methods	unsupported	Supported in constant functions
8. Classes
8.4 Objects (class instance)	non-synthesizable
8.5 Object properties and object parameter data	non-synthesizable
8.6 Object methods	non-synthesizable
8.7 Constructors	non-synthesizable
8.8 Typed constructor calls	non-synthesizable
8.9 Static class properties	non-synthesizable	Accessing static const properties to be supported in the future
8.10 Static methods	supported
8.11 This	non-synthesizable
8.12 Assignment, renaming, and copying	non-synthesizable
8.13 Inheritance and subclasses	supported
8.14 Overridden members	non-synthesizable
8.15 Super	non-synthesizable
8.16 Casting	non-synthesizable
8.17 Chaining constructors	non-synthesizable
8.18 Data hiding and encapsulation	non-synthesizable
8.19 Constant class properties	non-synthesizable	Accessing static const properties to be supported in the future
8.20 Virtual methods	non-synthesizable
8.21 Abstract classes and pure virtual methods	non-synthesizable
8.22 Polymorphism: dynamic method lookup	non-synthesizable
8.23 Class scope resolution operator ::	supported
8.24 Out-of-block declarations	supported
8.25 Parameterized classes	supported
8.26 Interface classes	supported
8.27 Typedef class	supported
9. Processes
9.2 Structured procedures	supported	final procedures ignored, initial procedures executed to initialize ROMs and variables
9.3 Block statements	supported	Parallel blocks (fork-join) non-synthesizable
9.4 Procedural timing controls	supported	Support is for synthesizable subset of timing controls in the opening of always, always_ff procedures Delay control (#1 etc.) non-synthesizable, pass --ignore-timing to ignore wait non-synthesizable iff unsupported
9.6 Process control	non-synthesizable
9.7 Fine-grain process control	non-synthesizable
10. Assignment statements	supported	Drive strength and charge strength non-synthesizable
10.3 Continuous assignments	supported
10.4 Procedural assignments	supported
10.5 Variable declaration assignment (variable initialization)	supported
10.6 Procedural continuous assignments	non-synthesizable
10.9 Assignment patterns	supported
10.10 Unpacked array concatenation	supported
10.11 Net aliasing	unsupported
11. Operators and expressions
11.3 Operators	supported	Operations on real operands non-synthesizable except in constant functions
11.4 Operator descriptions		See 11.3
11.6 Expression bit lengths	supported
11.7 Signed expressions	supported
11.8 Expression evaluation rules	supported
11.9 Tagged union expressions and member access	non-synthesizable
11.10 String literal expressions	supported
11.11 Minimum, typical, and maximum delay expressions	non-synthesizable
11.12 Let construct	supported
12. Procedural programming statements
12.4 Conditional if–else statement	no data
12.5 Case statement	no data
12.6 Pattern matching conditional statements	no data
12.7 Loop statements	no data
12.8 Jump statements	no data
13. Tasks and functions (subroutines)	no data
13.1 General	no data
13.2 Overview	no data
13.3 Tasks	no data
13.4 Functions	no data
13.5 Subroutine calls and argument passing	no data
13.6 Import and export functions	no data
13.7 Task and function names	no data
13.8 Parameterized tasks and functions	no data
14. Clocking blocks	no data
14.1 General	no data
14.2 Overview	no data
14.3 Clocking block declaration	no data
14.4 Input and output skews	no data
14.5 Hierarchical expressions	no data
14.6 Signals in multiple clocking blocks	no data
14.7 Clocking block scope and lifetime	no data
14.8 Multiple clocking blocks example	no data
14.9 Interfaces and clocking blocks	no data
14.10 Clocking block events	no data
14.11 Cycle delay: ##	no data
14.12 Default clocking	no data
14.13 Input sampling	no data
14.14 Global clocking	no data
14.15 Synchronous events	no data
14.16 Synchronous drives	no data
15. Interprocess synchronization and communication	no data
15.1 General	no data
15.2 Overview	no data
15.3 Semaphores	no data
15.4 Mailboxes	no data
15.5 Named events	no data
16. Assertions	no data
16.1 General	no data
16.2 Overview	no data
16.3 Immediate assertions	no data
16.4 Deferred assertions	no data
16.5 Concurrent assertions overview	no data
16.6 Boolean expressions	no data
16.7 Sequences	no data
16.8 Declaring sequences	no data
16.9 Sequence operations	no data
16.10 Local variables	no data
16.11 Calling subroutines on match of a sequence	no data
16.12 Declaring properties	no data
16.13 Multiclock support	no data
16.14 Concurrent assertions	no data
16.15 Disable iff resolution	no data
16.16 Clock resolution	no data
16.17 Expect statement	no data
16.18 Clocking blocks and concurrent assertions	no data
17. Checkers	no data
17.1 Overview	no data
17.2 Checker declaration	no data
17.3 Checker instantiation	no data
17.4 Context inference	no data
17.5 Checker procedures	no data
17.6 Covergroups in checkers	no data
17.7 Checker variables	no data
17.8 Functions in checkers	no data
17.9 Complex checker example	no data
18. Constrained random value generation	no data
18.1 General	no data
18.2 Overview	no data
18.3 Concepts and usage	no data
18.4 Random variables	no data
18.5 Constraint blocks	no data
18.6 Randomization methods	no data
18.7 In-line constraints—randomize() with	no data
18.8 Disabling random variables with rand_mode()	no data
18.9 Controlling constraints with constraint_mode()	no data
18.10 Dynamic constraint modification	no data
18.11 In-line random variable control	no data
18.12 Randomization of scope variables—std::randomize()	no data
18.13 Random number system functions and methods	no data
18.14 Random stability	no data
18.15 Manually seeding randomize	no data
18.16 Random weighted case—randcase	no data
18.17 Random sequence generation—randsequence	no data
19. Functional coverage	no data
19.1 General	no data
19.2 Overview	no data
19.3 Defining the coverage model: covergroup	no data
19.4 Using covergroup in classes	no data
19.5 Defining coverage points	no data
19.6 Defining cross coverage	no data
19.7 Specifying coverage options	no data
19.8 Predefined coverage methods	no data
19.9 Predefined coverage system tasks and system functions	no data
19.10 Organization of option and type_option members	no data
19.11 Coverage computation	no data
20. Utility system tasks and system functions	no data
20.1 General	no data
20.2 Simulation control system tasks	no data
20.3 Simulation time system functions	no data
20.4 Timescale system tasks	no data
20.5 Conversion functions	no data
20.6 Data query functions	no data
20.7 Array query functions	no data
20.8 Math functions	no data
20.9 Bit vector system functions	no data
20.10 Severity tasks	no data
20.11 Elaboration system tasks	no data
20.12 Assertion control system tasks	no data
20.13 Sampled value system functions	no data
20.14 Coverage system functions	no data
20.15 Probabilistic distribution functions	no data
20.16 Stochastic analysis tasks and functions	no data
20.17 Programmable logic array modeling system tasks	no data
20.18 Miscellaneous tasks and functions	no data
21. Input/output system tasks and system functions	no data
21.1 General	no data
21.2 Display system tasks	no data
21.3 File input/output system tasks and system functions	no data
21.4 Loading memory array data from a file	no data
21.5 Writing memory array data to a file	no data
21.6 Command line input	no data
21.7 Value change dump (VCD) files	no data
22. Compiler directives	no data
22.1 General	no data
22.2 Overview	no data
22.3 `resetall	no data
22.4 `include	no data
22.5 define, undef, and `undefineall	no data
22.6 ifdef, else, elsif, endif, `ifndef	no data
22.7 `timescale	no data
22.8 `default_nettype	no data
22.9 unconnected_drive and nounconnected_drive	no data
22.10 celldefine and endcelldefine	no data
22.11 `pragma	no data
22.12 `line	no data
22.13 __FILE__ and LINE	no data
22.14 begin_keywords, end_keywords	no data
23. Modules and hierarchy	no data
23.1 General	no data
23.2 Module definitions	no data
23.3 Module instances (hierarchy)	no data
23.4 Nested modules	no data
23.5 Extern modules	no data
23.6 Hierarchical names	no data
23.7 Member selects and hierarchical names	no data
23.8 Upwards name referencing	no data
23.9 Scope rules	no data
23.10 Overriding module parameters	no data
23.11 Binding auxiliary code to scopes or instances	no data
24. Programs	no data
24.1 General	no data
24.2 Overview	no data
24.3 The program construct	no data
24.4 Eliminating testbench races	no data
24.5 Blocking tasks in cycle/event mode	no data
24.6 Programwide space and anonymous programs	no data
24.7 Program control tasks	no data
25. Interfaces	no data
25.1 General	no data
25.2 Overview	no data
25.3 Interface syntax	no data
25.4 Ports in interfaces	no data
25.5 Modports	no data
25.6 Interfaces and specify blocks	no data
25.7 Tasks and functions in interfaces	no data
25.8 Parameterized interfaces	no data
25.9 Virtual interfaces	no data
25.10 Access to interface objects	no data
26. Packages	no data
26.1 General	no data
26.2 Package declarations	no data
26.3 Referencing data in packages	no data
26.4 Using packages in module headers	no data
26.5 Search order rules	no data
26.6 Exporting imported names from packages	no data
26.7 The std built-in package	no data
27. Generate constructs	no data
27.1 General	no data
27.2 Overview	no data
27.3 Generate construct syntax	no data
27.4 Loop generate constructs	no data
27.5 Conditional generate constructs	no data
27.6 External names for unnamed generate blocks	no data
28. Gate-level and switch-level modeling	no data
28.1 General	no data
28.2 Overview	no data
28.3 Gate and switch declaration syntax	no data
28.4 and, nand, nor, or, xor, and xnor gates	no data
28.5 buf and not gates	no data
28.6 bufif1, bufif0, notif1, and notif0 gates	no data
28.7 MOS switches	no data
28.8 Bidirectional pass switches	no data
28.9 CMOS switches	no data
28.10 pullup and pulldown sources	no data
28.11 Logic strength modeling	no data
28.12 Strengths and values of combined signals	no data
28.13 Strength reduction by nonresistive devices	no data
28.14 Strength reduction by resistive devices	no data
28.15 Strengths of net types	no data
28.16 Gate and net delays	no data
29. User-defined primitives	no data
29.1 General	no data
29.2 Overview	no data
29.3 UDP definition	no data
29.4 Combinational UDPs	no data
29.5 Level-sensitive sequential UDPs	no data
29.6 Edge-sensitive sequential UDPs	no data
29.7 Sequential UDP initialization	no data
29.8 UDP instances	no data
29.9 Mixing level-sensitive and edge-sensitive descriptions	no data
29.10 Level-sensitive dominance	no data
30. Specify blocks	no data
30.1 General	no data
30.2 Overview	no data
30.3 Specify block declaration	no data
30.4 Module path declarations	no data
30.5 Assigning delays to module paths	no data
30.6 Mixing module path delays and distributed delays	no data
30.7 Detailed control of pulse filtering behavior	no data
31. Timing checks	no data
31.1 General	no data
31.2 Overview	no data
31.3 Timing checks using a stability window	no data
31.4 Timing checks for clock and control signals	no data
31.5 Edge-control specifiers	no data
31.6 Notifiers: user-defined responses to timing violations	no data
31.7 Enabling timing checks with conditioned events	no data
31.8 Vector signals in timing checks	no data
31.9 Negative timing checks	no data
32. Backannotation using the standard delay format	no data
32.1 General	no data
32.2 Overview	no data
32.3 The SDF annotator	no data
32.4 Mapping of SDF constructs to SystemVerilog	no data
32.5 Multiple annotations	no data
32.6 Multiple SDF files	no data
32.7 Pulse limit annotation	no data
32.8 SDF to SystemVerilog delay value mapping	no data
32.9 Loading timing data from an SDF file	no data
33. Configuring the contents of a design	no data
33.1 General	no data
33.2 Overview	no data
33.3 Libraries	no data
33.4 Configurations	no data
33.5 Using libraries and configs	no data
33.6 Configuration examples	no data
33.7 Displaying library binding information	no data
33.8 Library mapping examples	no data
34. Protected envelopes	no data
34.1 General	no data
34.2 Overview	no data
34.3 Processing protected envelopes	no data
34.4 Protect pragma directives	no data
34.5 Protect pragma keywords	no data