No unknown modules

Starting with revision 3774661 the --ignore-unknown-modules option, which allowed instantiation of unknown (undefined) modules, will cease to be supported. Instead appropriate definitions need to be supplied for all modules which are part of the design hierarchy undergoing conversion to a netlist.

Rationale

Designs involving modules with unspecified port directions, port sizes and port types cannot be reliably elaborated. We don't wish to maintain this option going forward and request users to migrate to alternative solutions. The last revision supporting this option is b08e87c.

Suggested steps

If you were relying on --ignore-unknown-modules to instantiate technology primitives, or parts of the design written in another language, you will need to adjust your script or file list to load a blackbox definition of foreign modules in time for design elaboration. The definitions can come from one of the following sources:

Liberty files

If you have a .lib file describing available technology primitives, loading the library into Yosys as blackboxes with read_liberty -lib <filename> before the read_slang invocation will make those definitions visible at elaboration time. Depending on your library you may need to supply additional options to read_liberty for the library to be read successfully, typically -ignore_miss_func. See the read_liberty documentation.

SystemVerilog definitions in your file list

Blackbox definitions for technology primitives, or parts of the design written in a foreign language, can be part of the file list given to read_slang. For such definitions to be understood as defining blackboxes, rather than being an ordinary level of the design hierarchy, the module definition needs to

• be in a `celldefine ... `endcelldefine block, or
• have the (* blackbox *) attribute, or
• need to be empty apart from declaring ports, and at the same time the --empty-blackboxes option needs to be supplied to read_slang.

Other sources

Any definitions loaded into Yosys by the time read_slang is called are visible and can be instantiated from the SystemVerilog design hierarchy. One limitation is that such definitions don't allow setting parameters. If you need to set parameters, supply a .sv blackbox definition to read_slang directly instead of, or in addition to, loading a definition into Yosys ahead of read_slang.

Getting help

Please open a Discussion thread if you find this page incomplete, or not covering your use case.