[RV64_DYNAREC] Reduce instruction count for 64-bit addition carry flag - #4079
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ksco
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Jul 21, 2026
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You can move SET_FLAGS_NEZ(s5, F_CF, s4); to the else block and use OR(xFlags, xFlags, s5); in the if block to save 1 more instuction.
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Done. |
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The code is pretty obvious, so I think it's better to just remove those comments. |
…lag calculation Because CF flag reside in bit 0 of risc-v xFlags (x23), so we also can remove BEQZ inst for if block.
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Jul 21, 2026
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For the risc-v instruction
add rd, rs1, rs2, if an overflow occurs, only the lower XLEN bits of the sum are retained, and the resulting value will be numerically smaller than bothrs1andrs2.The combination of risc-v
addandsltuinstructions is commonly used to compute the carry flag of a 64-bit addition.