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Merged
colluca merged 6 commits into from
Dec 5, 2025
Merged

snitch-mempool proc added #32

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2ac8ddf
[LLVM/PULP] Separate the xpulpmacsi extension from xpulpv2
SamuelRiedel Nov 4, 2022
513561b
[LLVM/PULP] Separate the xpulppostmod extension from xpulpv2
SamuelRiedel Nov 7, 2022
962f566
[CLANG/RISCV] Separate xpulpv2 into subextensions
SamuelRiedel Apr 3, 2023
e0642c5
[LLVM/RISCV] Separate xpulpv2 into subextensions
SamuelRiedel Apr 3, 2023
5c479ef
fixup! [LLVM/RISCV] Separate xpulpv2 into subextensions
SamuelRiedel Apr 4, 2023
f00da9e
snitch-mempool proc added
Oct 17, 2025
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276 changes: 138 additions & 138 deletions clang/include/clang/Basic/BuiltinsRISCV.def
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11 changes: 11 additions & 0 deletions clang/test/CodeGen/RISCV/riscv-xpulpmacsi-intrinsics-diag.c
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// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 %s -triple=riscv32 -verify -S -o -

#include <stdint.h>

void test_builtin_pulp_diag(int32_t *data) {
// clang-format off
(void) __builtin_pulp_mac(1, 2, 3); // expected-error {{builtin requires at least one of the following extensions support to be enabled : 'Xpulpv', 'Xpulpmacsi'}}
(void) __builtin_pulp_msu(1, 2, 10); // expected-error {{builtin requires at least one of the following extensions support to be enabled : 'Xpulpv', 'Xpulpmacsi'}}
// clang-format on
}
39 changes: 39 additions & 0 deletions clang/test/CodeGen/RISCV/riscv-xpulpmacsi-intrinsics.c
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// REQUIRES: riscv-registered-target
// Performing the same checks for each possible way to invoke clang
// for PULP extensions:
// 1. cc1 with unversioned group extension (+xpulpv instead of +xpulpv2)
// RUN: %clang_cc1 -triple riscv32 -target-feature +xpulpv -emit-llvm %s -o - \
// RUN: | FileCheck %s
// 2. clang with versioned group extension
// RUN: %clang --target=riscv32 -march=rv32imafcxpulpv2 -c -S -emit-llvm %s -o - \
// RUN: | FileCheck %s
// 3. clang with specific extension
// RUN: %clang --target=riscv32 -march=rv32imafcxpulpmacsi -c -S -emit-llvm %s -o - \
// RUN: | FileCheck %s
// 4. clang with a platform triple that is expected to provide PULP extensions
// RUN: %clang --target=riscv32-hero-unknown-elf -c -S -emit-llvm %s -o - \
// RUN: | FileCheck %s

#include <stdint.h>

typedef int16_t v2s __attribute__((vector_size(4)));
typedef uint16_t v2u __attribute__((vector_size(4)));
typedef int8_t v4s __attribute__((vector_size(4)));
typedef uint8_t v4u __attribute__((vector_size(4)));

// CHECK-LABEL: @test_builtin_pulp_mac(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.riscv.pulp.mac(i32 1, i32 2, i32 3)
// CHECK-NEXT: ret i32 [[RES]]
int32_t test_builtin_pulp_mac(void) {
return __builtin_pulp_mac(1, 2, 3);
}

// CHECK-LABEL: @test_builtin_pulp_msu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.riscv.pulp.msu(i32 1, i32 2, i32 10)
// CHECK-NEXT: ret i32 [[RES]]
//
int32_t test_builtin_pulp_msu(void) {
return __builtin_pulp_msu(1, 2, 10);
}
17 changes: 17 additions & 0 deletions clang/test/CodeGen/RISCV/riscv-xpulppostmod-intrinsics-diag.c
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// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 %s -triple=riscv32 -verify -S -o -

#include <stdint.h>

void test_builtin_pulp_diag(int32_t *data) {
// clang-format off
(void) __builtin_pulp_OffsetedRead(data, 4); // expected-error {{builtin requires at least one of the following extensions support to be enabled : 'Xpulpv', 'Xpulppostmod'}}
(void) __builtin_pulp_OffsetedReadHalf((int16_t *) data, 4); // expected-error {{builtin requires at least one of the following extensions support to be enabled : 'Xpulpv', 'Xpulppostmod'}}
(void) __builtin_pulp_OffsetedReadByte((char *) data, 4); // expected-error {{builtin requires at least one of the following extensions support to be enabled : 'Xpulpv', 'Xpulppostmod'}}
__builtin_pulp_OffsetedWrite(1, data, 4); // expected-error {{builtin requires at least one of the following extensions support to be enabled : 'Xpulpv', 'Xpulppostmod'}}
__builtin_pulp_OffsetedWriteHalf(1, (int16_t *) data, 4); // expected-error {{builtin requires at least one of the following extensions support to be enabled : 'Xpulpv', 'Xpulppostmod'}}
__builtin_pulp_OffsetedWriteByte(1, (char *) data, 4); // expected-error {{builtin requires at least one of the following extensions support to be enabled : 'Xpulpv', 'Xpulppostmod'}}
(void) __builtin_pulp_read_base_off(data, 0xF); // expected-error {{builtin requires at least one of the following extensions support to be enabled : 'Xpulpv', 'Xpulppostmod'}}
__builtin_pulp_write_base_off(0x1, data, 0xF); // expected-error {{builtin requires at least one of the following extensions support to be enabled : 'Xpulpv', 'Xpulppostmod'}}
// clang-format on
}
81 changes: 81 additions & 0 deletions clang/test/CodeGen/RISCV/riscv-xpulppostmod-intrinsics.c
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// REQUIRES: riscv-registered-target
// Performing the same checks for each possible way to invoke clang
// for PULP extensions:
// 1. cc1 with unversioned group extension (+xpulpv instead of +xpulpv2)
// RUN: %clang_cc1 -triple riscv32 -target-feature +xpulpv -emit-llvm %s -o - \
// RUN: | FileCheck %s
// 2. clang with versioned group extension
// RUN: %clang --target=riscv32 -march=rv32imafcxpulpv2 -c -S -emit-llvm %s -o - \
// RUN: | FileCheck %s
// 3. clang with specific extension
// RUN: %clang --target=riscv32 -march=rv32imafcxpulppostmod -c -S -emit-llvm %s -o - \
// RUN: | FileCheck %s
// 4. clang with a platform triple that is expected to provide PULP extensions
// RUN: %clang --target=riscv32-hero-unknown-elf -c -S -emit-llvm %s -o - \
// RUN: | FileCheck %s

#include <stdint.h>

// CHECK-LABEL: @test_builtin_pulp_OffsetedRead(
// CHECK: [[PTR:%.*]] = load i32*, i32** %data.addr, align 4
// CHECK: [[RES:%.*]] = call i32 @llvm.riscv.pulp.OffsetedRead(i32* [[PTR]], i32 4)
//
int32_t test_builtin_pulp_OffsetedRead(int32_t *data) {
return __builtin_pulp_OffsetedRead(data, 4);
}

// CHECK-LABEL: @test_builtin_pulp_OffsetedWrite(
// CHECK: [[PTR:%.*]] = load i32*, i32** %data.addr, align 4
// CHECK: call void @llvm.riscv.pulp.OffsetedWrite(i32 1, i32* [[PTR]], i32 4)
//
void test_builtin_pulp_OffsetedWrite(int32_t *data) {
__builtin_pulp_OffsetedWrite(1, data, 4);
}

// CHECK-LABEL: @test_builtin_pulp_OffsetedReadHalf(
// CHECK: [[PTR:%.*]] = load i16*, i16** %data.addr, align 4
// CHECK: [[RES:%.*]] = call i32 @llvm.riscv.pulp.OffsetedReadHalf(i16* [[PTR]], i32 4)
//
int16_t test_builtin_pulp_OffsetedReadHalf(int16_t *data) {
return __builtin_pulp_OffsetedReadHalf(data, 4);
}

// CHECK-LABEL: @test_builtin_pulp_OffsetedWriteHalf(
// CHECK: [[PTR:%.*]] = load i16*, i16** %data.addr, align 4
// CHECK: call void @llvm.riscv.pulp.OffsetedWriteHalf(i32 1, i16* [[PTR]], i32 4)
//
void test_builtin_pulp_OffsetedWriteHalf(int16_t *data) {
__builtin_pulp_OffsetedWriteHalf(1, data, 4);
}

// CHECK-LABEL: @test_builtin_pulp_OffsetedReadByte(
// CHECK: [[PTR:%.*]] = load i8*, i8** %data.addr, align 4
// CHECK: [[RES:%.*]] = call i32 @llvm.riscv.pulp.OffsetedReadByte(i8* [[PTR]], i32 4)
//
char test_builtin_pulp_OffsetedReadByte(char *data) {
return __builtin_pulp_OffsetedReadByte(data, 4);
}

// CHECK-LABEL: @test_builtin_pulp_OffsetedWriteByte(
// CHECK: [[PTR:%.*]] = load i8*, i8** %data.addr, align 4
// CHECK: call void @llvm.riscv.pulp.OffsetedWriteByte(i32 1, i8* [[PTR]], i32 4)
//
void test_builtin_pulp_OffsetedWriteByte(char *data) {
__builtin_pulp_OffsetedWriteByte(1, data, 4);
}

// CHECK-LABEL: @test_builtin_pulp_read_base_off(
// CHECK: [[PTR:%.*]] = load i32*, i32** %data.addr, align 4
// CHECK: call i32 @llvm.riscv.pulp.read.base.off(i32* [[PTR]], i32 15)
//
int32_t test_builtin_pulp_read_base_off(int32_t* data) {
return __builtin_pulp_read_base_off(data, 0xF);
}

// CHECK-LABEL: @test_builtin_pulp_write_base_off(
// CHECK: [[PTR:%.*]] = load i32*, i32** %data.addr, align 4
// CHECK: call void @llvm.riscv.pulp.write.base.off(i32 1, i32* [[PTR]], i32 15)
//
void test_builtin_pulp_write_base_off(int32_t* data) {
__builtin_pulp_write_base_off(0x1, data, 0xF);
}
1 change: 1 addition & 0 deletions llvm/include/llvm/Support/RISCVTargetParser.def
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Expand Up @@ -33,5 +33,6 @@ PROC(SIFIVE_S76, {"sifive-s76"}, FK_64BIT, {"rv64gc"})
PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"})
PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})
PROC(SNITCH, {"snitch"}, FK_NONE, {"rv32imafd_zfh_xfrep_xssr_xdma_xcopift_xfalthalf_xfquarter_xfaltquarter_xfvecsingle_xfvechalf_xfvecalthalf_xfvecquarter_xfvecaltquarter_xfauxhalf_xfauxalthalf_xfauxquarter_xfauxaltquarter_xfauxvecsingle_xfauxvechalf_xfauxvecalthalf_xfauxvecquarter_xfauxvecaltquarter_xfexpauxvechalf_xfexpauxvecalthalf_xfexpauxvecquarter_xfexpauxvecaltquarter"})
PROC(SNITCH_MEMPOOL, {"snitch-mempool"}, FK_NONE, {"rv32imafd_zfh_xfalthalf_xfquarter_xfaltquarter_xfvecsingle_xfvechalf_xfvecalthalf_xfvecquarter_xfvecaltquarter_xfauxhalf_xfauxalthalf_xfauxquarter_xfauxaltquarter_xfauxvecsingle_xfauxvechalf_xfauxvecalthalf_xfauxvecquarter_xfauxvecaltquarter_xfexpauxvechalf_xfexpauxvecalthalf_xfexpauxvecquarter_xfexpauxvecaltquarter_xpulpabs_xpulpbitop_xpulpbr_xpulpclip_xpulpmacsi_xpulpminmax_xpulppostmod_xpulpslet_xpulpvect_xpulpvectshufflepack"})

#undef PROC
21 changes: 21 additions & 0 deletions llvm/lib/Support/RISCVISAInfo.cpp
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Expand Up @@ -125,6 +125,27 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"xfexpauxvecaltquarter", RISCVExtensionVersion{0, 1}},
// PULP extensions
{"xpulpv", RISCVExtensionVersion{2, 0}},
{"xpulphwloop", RISCVExtensionVersion{0, 1}},
{"xpulppostmod", RISCVExtensionVersion{0, 1}},
{"xpulpindregreg", RISCVExtensionVersion{0, 1}},
{"xpulpelw", RISCVExtensionVersion{0, 1}},
{"xpulpabs", RISCVExtensionVersion{0, 1}},
{"xpulpslet", RISCVExtensionVersion{0, 1}},
{"xpulpmacsi", RISCVExtensionVersion{0, 1}},
{"xpulpmulrnhi", RISCVExtensionVersion{0, 1}},
{"xpulpmacrnhi", RISCVExtensionVersion{0, 1}},
{"xpulppartmac", RISCVExtensionVersion{0, 1}},
{"xpulpminmax", RISCVExtensionVersion{0, 1}},
{"xpulpbitop", RISCVExtensionVersion{0, 1}},
{"xpulpvect", RISCVExtensionVersion{0, 1}},
{"xpulpvectshufflepack", RISCVExtensionVersion{0, 1}},
{"xpulpvectcomplex", RISCVExtensionVersion{0, 1}},
{"xpulpclip", RISCVExtensionVersion{0, 1}},
{"xpulpaddsubrn", RISCVExtensionVersion{0, 1}},
{"xpulpbr", RISCVExtensionVersion{0, 1}},
{"xpulpbitrev", RISCVExtensionVersion{0, 1}},
{"xpulpvectgap8", RISCVExtensionVersion{0, 1}},
{"xpulpvectgap9", RISCVExtensionVersion{0, 1}},
};

static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
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Expand Up @@ -1934,7 +1934,7 @@ RISCVAsmParser::parseMemOpBaseReg(OperandVector &Operands) {
return MatchOperand_ParseFail;
}

if (getSTI().getFeatureBits()[RISCV::FeaturePULPExtV2]) {
if (getSTI().getFeatureBits()[RISCV::FeaturePULPExtPostmod]) {
if (getLexer().is(AsmToken::Exclaim)){
getParser().Lex(); // Eat '!'
Operands.push_back(RISCVOperand::createToken("!", getLoc(), isRV64()));
Expand Down Expand Up @@ -2035,7 +2035,7 @@ bool RISCVAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {

// Attempt to parse token as a register.
if (parseRegister(Operands, true) == MatchOperand_Success) {
if (getSTI().getFeatureBits()[RISCV::FeaturePULPExtV2]) {
if (getSTI().getFeatureBits()[RISCV::FeaturePULPExtPostmod]) {
if (getLexer().is(AsmToken::LParen))
return parseMemOpBaseReg(Operands) != MatchOperand_Success;
}
Expand Down
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