[VLSU] Fix: vlsu read ports connection misordered

[bowwwang]

Summary

This PR fixes a misconnection of VLSU VRF read ports in the top-level spatz.sv.
The issue affects indexed load/store instructions, where the vector register used as the index is incorrectly wired.

The fix is limited to top-level wiring changes and does not modify any VLSU internal logic.

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Motivation / Reason

• In spatz_vlsu.sv, the vrf_r interface exposes two read ports to support indexed load/store instructions.

• Inspecting spatz_vlsu.sv (around line 784) shows that the MSB bit of the VRF read port selection is used for the index register.

• However, in the top-level spatz.sv:

  • Lines 428–432 assign the MSB bits to vd.
  • This contradicts RVV semantics, where rs2 (vs2) must be used as the index register for indexed load/store instructions.

• As a result, vd and vs2 are misconnected when wiring the VLSU VRF read ports at the top level.

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Fix Strategy

• The simplest and safest fix is to swap the VRF read port wiring in spatz.sv so that:

  • The MSB read port is connected to vs2 (index register)
  • The other read port is connected to vd

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Files Changed

• hw/ip/spatz/src/spatz.sv

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Diff Overview

This commit swaps the order of VRF read-related signals (raddr, re, rdata, rvalid, and id) so that vs2 is correctly mapped as the index register instead of vd.

No functional changes outside of wiring reordering are introduced.

[Navaneeth-KunhiPurayil]

Looks good to me. Thanks for the fix!