Add tc_clk_or2 And Add Warning About tc_clk_mux2 Usage #27
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meggiman
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This PR adds a new generic clock gate cell (OR-gate) to the
tc_clk.svcell family. Furthermore, I added a warning about the limitations of thetc_clk_mux2cell in common standard cell libraries. They are not glitch-free and must not be used for dynamic switching between two clocks without any additional precautionary steps.