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Track B already does the hard, right thing: VCR-ISA-001 re-bases the ARM/RISC-V semantics on Sail-generated Rocq (coq/Synth/ARM/SailArmBridge.v, 92 Qed), ArmRefinement.v states refinement to the official Sail semantics, and #667 landed "generate, don't mirror" so the selector model is generated rather than hand-copied. This issue is not "adopt Sail" — it is the third leg of Sail's own validation methodology, which we do not yet have:
Measure coverage of the semantics model itself, and treat uncovered model code as unvalidated semantics.
Why, in one sentence
#682 is the canonical case: rule_i32_shl_correct carried a green Rocq Qed, yet the shipped thumb-2 code silently miscompiled shift amounts ≥32 — because ArmSemantics.v modelled LSL_reg as x << (amount mod 32), i.e. Wasm's masking, not ARMv7-M's Rm[7:0] behaviour. The proof was fine; the model was unfaithful; the proof was therefore vacuous against silicon, and only qemu differential execution caught it. Generating from Sail closes the authorship half of that. It does not tell us which parts of the semantics our proofs actually exercise — and the unexercised parts are precisely where the next #682 lives.
The prior art
Armstrong et al., ISA Semantics for ARMv8-A, RISC-V, and CHERI-MIPS, POPL 2019 (PDF), §7 Validation. Three mechanisms, and we currently have one:
Sail's mechanism
synth today
Provenance — auto-translate from the vendor's authoritative ASL, not a re-reading of the manual
✅ SailArmBridge.v / VCR-ISA-001
Differential validation at scale — ARM's Architecture Validation Suite, "over 30 000 test programs … billions of instructions"; residual mismatches individually triaged (24 of 15 400, 0.15%)
⚠️ partial — we differential-test our compiler output on qemu/silicon, not the model against a vendor suite
Coverage of the model — which parts of the ISA semantics are actually exercised
❌ missing
The wider survey result is the honest framing to keep: "is my semantics model faithful?" has no formal solution. There is no mechanical adequacy metric for a semantics model — the state of the art is provenance + differential validation + model coverage. So this issue proposes the best available engineering answer, not a proof.
Proposed
Coverage instrumentation over the generated ISA model. For every proved selection rule, record which Sail-derived semantic definitions its proof/evaluation touches. Publish a per-target model-coverage.json.
Report the complement loudly. The valuable artifact is the uncovered set: "these ISA behaviours are in the model, and no proof or test exercises them" = the candidate list for the next silent miscompile. Mirrors Kind 2's --print_ivc_complement (Inductive Validity Cores, arXiv:1603.04276) — proof-core coverage generalized to software; treat everything the proof did not need as unverified.
Vendor-suite differential (stretch). Where licensing permits, run the model against ARM's compliance suite as Sail does, rather than only checking our emitted code. This is the leg with the biggest gap between us and the reference methodology.
Not a regression report
#682 and #776 are closed and fixed. This is about the class, not those instances: closing individual vacuity holes is O(n); measuring model coverage is the mechanism that finds them before shipping.
Ask
Track B already does the hard, right thing:
VCR-ISA-001re-bases the ARM/RISC-V semantics on Sail-generated Rocq (coq/Synth/ARM/SailArmBridge.v, 92 Qed),ArmRefinement.vstates refinement to the official Sail semantics, and #667 landed "generate, don't mirror" so the selector model is generated rather than hand-copied. This issue is not "adopt Sail" — it is the third leg of Sail's own validation methodology, which we do not yet have:Why, in one sentence
#682 is the canonical case:
rule_i32_shl_correctcarried a green RocqQed, yet the shipped thumb-2 code silently miscompiled shift amounts ≥32 — becauseArmSemantics.vmodelledLSL_regasx << (amount mod 32), i.e. Wasm's masking, not ARMv7-M'sRm[7:0]behaviour. The proof was fine; the model was unfaithful; the proof was therefore vacuous against silicon, and only qemu differential execution caught it. Generating from Sail closes the authorship half of that. It does not tell us which parts of the semantics our proofs actually exercise — and the unexercised parts are precisely where the next #682 lives.The prior art
Armstrong et al., ISA Semantics for ARMv8-A, RISC-V, and CHERI-MIPS, POPL 2019 (PDF), §7 Validation. Three mechanisms, and we currently have one:
SailArmBridge.v/ VCR-ISA-001The wider survey result is the honest framing to keep: "is my semantics model faithful?" has no formal solution. There is no mechanical adequacy metric for a semantics model — the state of the art is provenance + differential validation + model coverage. So this issue proposes the best available engineering answer, not a proof.
Proposed
model-coverage.json.--print_ivc_complement(Inductive Validity Cores, arXiv:1603.04276) — proof-core coverage generalized to software; treat everything the proof did not need as unverified.ArmSemantics.v) rather than the Sail-derived one, make that visible as an explicit, counted trusted-base entry — a hand-simplified model standing in for the authoritative one is exactly the thumb-2: i32.shl/shr_s/shr_u don't mask the shift amount mod 32 — amounts >=32 silently compile to 0 (VCR-SEL regression; Rocq ARM model masks like WASM so proof is vacuous) #682 shape, and it should be a number that can only shrink.Not a regression report
#682 and #776 are closed and fixed. This is about the class, not those instances: closing individual vacuity holes is O(n); measuring model coverage is the mechanism that finds them before shipping.