v0.30.2 — A32 i64 silent-NOP class ends (#615)

Every A32 (--target cortex-r5) i64 op computed real results — the entire family was silently encoding to NOP (#615). The silent-NOP class (#594 → #610 → #615) ends here.

Fixed

• A32 i64 mul/shifts/rotates/all-10-comparisons/eqz/clz/ctz/popcnt/div/rem/const/load/store/extends — plus i32 SetCond/SelectMove/Popcnt — encoded as the literal NOP word on cortex-r5 (#615, PR #620). All now expand via encode_arm_expanded mirroring each Thumb-2 twin's register contract; div/rem get A32 fixed-ABI wrappers with the zero-divisor UDF trap. Ops no A32 target can legally reach are typed Err — loud, never NOP.
• Evidence: 24/24 clang bit-exact encoding cross-checks, branch-offset audit, 352-case ARM-mode unicorn-vs-wasmtime differential (pre-fix: 254 mismatches; post-fix: 0), frozen anchors 9/9 byte-identical (Thumb untouched).

Added

• Structural tripwire a32_no_silent_nop_615.rs: exhaustive no-wildcard match over all 221 ArmOp variants — a new variant fails compilation until classified; the class cannot silently regrow.

Changed

• deps: rivet 0.24.0, ordeal 0.4.2, scry-sai-core 3.0.0.

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