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Centralize soc_to_chipset map #6033

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13 changes: 5 additions & 8 deletions backends/qualcomm/tests/utils.py
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Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,10 @@
from executorch.backends.qualcomm.serialization.qnn_compile_spec_schema import (
QcomChipset,
)
from executorch.backends.qualcomm.utils.utils import capture_program
from executorch.backends.qualcomm.utils.utils import (
capture_program,
get_soc_to_chipset_map,
)
from executorch.devtools import generate_etrecord, Inspector
from executorch.examples.qualcomm.utils import (
generate_inputs,
Expand Down Expand Up @@ -117,13 +120,7 @@ class TestQNN(unittest.TestCase):
build_folder: Literal = ""
model: QcomChipset = None
compiler_specs: List[CompileSpec] = None
arch_table = {
"SSG2115P": QcomChipset.SSG2115P,
"SM8650": QcomChipset.SM8650,
"SM8550": QcomChipset.SM8550,
"SM8475": QcomChipset.SM8475,
"SM8450": QcomChipset.SM8450,
}
arch_table = get_soc_to_chipset_map()
error_only = False
ip = "localhost"
port = 8080
Expand Down
10 changes: 10 additions & 0 deletions backends/qualcomm/utils/utils.py
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Expand Up @@ -850,3 +850,13 @@ def generate_qnn_executorch_compiler_spec(
QCOM_QNN_COMPILE_SPEC, convert_to_flatbuffer(qnn_executorch_options)
)
]


def get_soc_to_chipset_map():
return {
"SSG2115P": QcomChipset.SSG2115P,
"SM8650": QcomChipset.SM8650,
"SM8550": QcomChipset.SM8550,
"SM8475": QcomChipset.SM8475,
"SM8450": QcomChipset.SM8450,
}
12 changes: 2 additions & 10 deletions examples/qualcomm/oss_scripts/llama2/llama.py
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Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,7 @@
convert_linear_to_conv2d,
generate_htp_compiler_spec,
generate_qnn_executorch_compiler_spec,
get_soc_to_chipset_map,
)
from executorch.examples.qualcomm.oss_scripts.llama2.model.static_llama import (
LlamaModel,
Expand All @@ -47,15 +48,6 @@
from torch.ao.quantization.quantize_pt2e import convert_pt2e, prepare_pt2e


soc_to_chipset_map = {
"SSG2115P": QcomChipset.SSG2115P,
"SM8650": QcomChipset.SM8650,
"SM8550": QcomChipset.SM8550,
"SM8475": QcomChipset.SM8475,
"SM8450": QcomChipset.SM8450,
}


pte_filename = "llama2_qnn"


Expand Down Expand Up @@ -402,7 +394,7 @@ def compile(args):
end_quantize_ts = time.time()
print("single_llama.quantize(quant_dtype)", end_quantize_ts - start_quantize_ts)
single_llama.lowering_modules(
args.artifact, kv_type=kv_type, soc_model=soc_to_chipset_map[args.model]
args.artifact, kv_type=kv_type, soc_model=get_soc_to_chipset_map[args.model]
)
end_lowering_ts = time.time()
print("Complete Compile", end_lowering_ts - end_quantize_ts)
Expand Down
10 changes: 2 additions & 8 deletions examples/qualcomm/utils.py
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Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,7 @@
capture_program,
generate_htp_compiler_spec,
generate_qnn_executorch_compiler_spec,
get_soc_to_chipset_map,
)
from executorch.exir import EdgeCompileConfig, EdgeProgramManager, to_edge
from executorch.exir.backend.backend_api import to_backend
Expand Down Expand Up @@ -82,14 +83,7 @@ def __init__(
self.dump_intermediate_outputs = dump_intermediate_outputs
self.debug_output_path = f"{self.workspace}/debug_output.bin"
self.output_folder = f"{self.workspace}/outputs"
self.arch_table = {
"SSG2115P": "73",
"SM8650": "75",
"SM8550": "73",
"SM8475": "69",
"SM8450": "69",
}
self.soc_model = self.arch_table[soc_model]
self.soc_model = get_soc_to_chipset_map()[soc_model]
self.error_only = error_only
self.shared_buffer = shared_buffer
self.runner = runner
Expand Down
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