Update the torch-xpu-ops commit to [intel/torch-xpu-ops@1a3415](https://github.com/intel/torch-xpu-ops/commit/1a3415a46d2486569b0b6da4446e0284cbf3591e):

- Avoid register spilling in elementwise ops for mixed fp32/bf16/fp16 inputs by adding vectorized type-casting loads
- Fix group_reduce assert on XPU to avoid incorrect aborting
- Fix undefined behavior caused by NaN input for TopK
- Fix fused moving-avg observer/fake-quant dtype mismatches on XPU
- Remove host compiler for SYCL and use pure SYCL compilation
Pull Request resolved: https://github.com/pytorch/pytorch/pull/194185
Approved by: https://github.com/EikanWang