7.2 optee - #1019
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… voltage for SD-card SD cards may need 1.8v VDDIO also to be supported, to accommodate this requirement reduce the min voltage to 1.8v for `vreg_l2b_e0` which supplies to VDDIO pin of SD card. NOTE - Since this SD card is the only client on this regulator, this change should not have any side effect on any other clients. moreover, SD card driver takes care to explicitly vote for the regulator voltage based on the SD card detection sequence. Also for stable operation of the SD card increase VDD voltage supplied by `vreg_l9b_e0` to 2.96v. Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com> Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260702094056.3755467-2-mchunara@oss.qualcomm.com/ Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
Document the Glymur-specific SDHCI compatible in the sdhci-msm binding. Use "qcom,sdhci-msm-v5" as the fallback compatible for the MSM SDHCI v5 controller used on Glymur. Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260703-loutish-stimulating-hummingbird-aada5e@quoll/ Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
Add support for SD card on Glymur SoC and enable the required pinctrl configurations. Co-developed-by: Sachin Rathore <sachin.rathore@oss.qualcomm.com> Signed-off-by: Sachin Rathore <sachin.rathore@oss.qualcomm.com> Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260702094056.3755467-4-mchunara@oss.qualcomm.com/ Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
Enable SD card for Glymur CRD platform. Configure the vmmc/vqmmc regulators and gpio-based card detection for the platform. Co-developed-by: Sachin Rathore <sachin.rathore@oss.qualcomm.com> Signed-off-by: Sachin Rathore <sachin.rathore@oss.qualcomm.com> Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260702094056.3755467-5-mchunara@oss.qualcomm.com/ Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
The traceNoC node is the system-level Aggregator TNOC, so it must own a valid ATID that tags the whole aggregation path. It was marked compatible with "qcom,coresight-itnoc", an Interconnect TNOC, which is never assigned an ATID. As a result the aggregator had no trace ID and could not tag the merged trace. An Interconnect TNOC is a subsystem-level aggregator: it merges trace from the ATB sources within its subsystem (TPDMs and other ATB masters) and forwards the combined stream to the system-level Aggregator TNOC. It carries no ATID of its own, because the Aggregator TNOC downstream in the path already owns the ATID. Switch the node to "qcom,coresight-tnoc" so it is described as the Aggregator TNOC it is and is assigned a system trace ID. Rename the node to "tn" and use the "apb_pclk" clock name as required by the Aggregator TNOC binding. Link: https://lore.kernel.org/all/20260710-fix-tracenoc-probe-issue-v6-5-41eb36fef8d9@oss.qualcomm.com/ Fixes: 1f7d0c4 ("arm64: dts: qcom: glymur: add coresight nodes") Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Embedded Trace Router(ETR) is working as a DDR memory sink to collect tracing data from source device and the CTCU device serves as the control unit for the ETR device. Link: https://lore.kernel.org/all/20260714-add-ctcu-etr-for-glymur-v1-1-791de63c0713@oss.qualcomm.com/ Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
According to user manual / programming guide there is no separate PCIe phy 3A and 3B, but one 8-lane QMP PCIe Gen5 PHY which consists of two 4-lane blocks. This is also visible in memory map, where the 0xf00000 is marked as the main block with additional sub blocks for each 4-lane phys. Describing the sub phys without the rest is not correct from hardware description, even if it works. Link: https://lore.kernel.org/all/20260609141608.354186-2-krzysztof.kozlowski@oss.qualcomm.com/ Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Glymur's PCIe3a and PCIe3b controllers share a single Gen5x8 QMP PHY block that can be bifurcated into two independent x4 links, rather than each controller owning its own dedicated PHY. Add a pcie3_phy node describing the shared PHY block, add the missing PCIe3a controller node, and point both PCIe3a's and PCIe3b's port phys at &pcie3_phy (index 0 and 1 respectively) so each controller picks up its half of the bifurcated PHY. Update the GCC pipe clock parent array to reference the new PHY's clock outputs instead of the placeholders. Link: https://lore.kernel.org/all/20260717-glymur_linkmode_0717-v5-0-4f9e87a61463@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
CRD wires the shared Gen5x8 PCIe PHY's regulator supplies through board-specific PMIC rails. Add the vdda-phy, vdda-pll, and vdda-refgen0p9/1p2 supplies for &pcie3_phy. Link: https://lore.kernel.org/all/20260717-glymur_linkmode_0717-v5-0-4f9e87a61463@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Add PCIe3a required resources eg. power supplies, GPIOs. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Enable PCIe3b controller and PCIe3b PHY. Add required LDOs and GPIOs. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
The currently listed SoCCP and SoCCP DTB reserved memory regions don't align with the memory requested by the SoCCP Firmware. Fix this by updating the SoCCP/SoCCP DTB memory regions to reflect the memory region requirements of the SoCCP firmware, as described in the Glymur v21 memory map release. Link: https://lore.kernel.org/lkml/20260709-glymur-soccp-v6-3-16f70227547d@oss.qualcomm.com/ Fixes: 41b6e8d ("arm64: dts: qcom: Introduce Glymur base dtsi") Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
…ng system resume On Glymur, display NoC errors are observed during system resume when MDSS register accesses occur before the MMCX/Display NoC path has scaled back to a voltage level sufficient for the required bandwidth. Keep the display clock controller's power-domain requirement at the turbo operating point as a temporary workaround to ensure the interconnect remains at a stable performance level during the resume sequence and avoid NoC errors triggered by early MDSS register access. Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Add Battery Current Limiting (BCL) hardware monitor node for pmh0101 PMIC. The BCL monitors battery voltage and current, providing hardware interrupts when configurable thresholds are violated. Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260722-qcom-bcl-hwmon-v2-6-febe2805e17b@oss.qualcomm.com
Add Battery Current Limiting (BCL) hardware monitor node for smb2370 PMIC. The BCL monitors battery voltage and current, providing hardware interrupts when configurable thresholds are violated. Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260722-qcom-bcl-hwmon-v2-10-febe2805e17b@oss.qualcomm.com
This reverts commit 2d19aee. Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
Add iris video codec to glymur SoC, which comes with significantly different powering up sequence than previous platforms, thus different clocks and resets. https://lore.kernel.org/all/20260726-glymur-v10-13-de451559e88b@oss.qualcomm.com Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Tested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
The iris hardware block is described in the glymur SoC DTSI, and enabling it here allows the media iris driver to probe and use the video codec functionality. Link: https://lore.kernel.org/all/20260726-glymur-v10-14-de451559e88b@oss.qualcomm.com Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
On Glymur, there is an issue while working with the FP sensor connected to USB Hs only controller. The issue is as follows: 1) During boot, the usb controller initialises fine, but an error stating that the descriptor read from FP sensor failed and hence the controller is in an unknown state with failed enumeration of FP sensor. 2) At this point, the problem may be resource voting, but if unbind and rebind is done on the controller, enumeration is fine. All resources were thorughly checked and also schematic was checked to ensure that no GPIOs (if any) are left un-initialised. But resources seem to be fine. 3) When in this state, if we try to enter system suspend, GDSC too gets off, and also on resume we see that usb controller goes dead. And further attempts to enter suspend are gated by this dead controller. 4) If we re-bind controller on boot and then let enumration be successful, and then enter suspend, we see a SMMU crash on resume. On upstream code however, enumeration is fine on every reboot. This suspend-resume behavior is gating XO SD and hence disable it on CRD. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Signed-off-by: Pratham Pratap <pratham.pratap@oss.qualcomm.com>
…s node The High-speed only controller is DRD capable. Hence move the dr_mode property to platform DTS and mark the controller as role switch capable. While at it, since its high-speed only controller, disable pipe clock requirement. Link: https://lore.kernel.org/all/20260723-glymur-usb-fixes-v1-1-816357d5319c@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
…eup-capable All USB controller on Glymur are wakeup-capable device. Add wakeup-source property for each of them indicating the same. Link: https://lore.kernel.org/all/20260723-glymur-usb-fixes-v1-2-816357d5319c@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Add the ADC channels under the PMK8850 ADC node for the other PMICS on the board with ADC peripherals. This includes die temperature and VPH power channels per PMIC. Add a thermal zone corresponding to the PMK8850 xo_therm ADC thermistor channel to enable temperature monitoring. Also add io-channels and io-channel-names properties to the temp_alarm nodes so that they can get temperature reading from the newly added ADC die_temp channels. Link: https://lore.kernel.org/all/20260731-pmic5_gen4_adc-v1-6-9c49b2eea6f9@oss.qualcomm.com/ Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Add the missing SIDs for the LPASS eNPU masters to the ADSP iommus list. These masters are exercised during audio record use cases where Environmental Acoustic Intelligence (EAI) models run on the eNPUs. Currently all transactions from these eNPU masters will result in global faults; fix them by adding the additional SIDs. Link: https://lore.kernel.org/lkml/20260811-adsp-smmu-fix-v1-1-a596d284c455@oss.qualcomm.com/ Fixes: cd1d174 ("arm64: dts: qcom: glymur: Add ADSP and CDSP for Glymur SoC") Signed-off-by: Sairamreddy Bojja <sairamreddy.bojja@oss.qualcomm.com> Co-developed-by: Iranna Mundaganur <iranna.mundaganur@oss.qualcomm.com> Signed-off-by: Iranna Mundaganur <iranna.mundaganur@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Introduce support for the Qualcomm Kalambo SoC. It is derived from Mahua with CPU cluster 0 (cpu0-cpu5) removed, leaving only cluster 1 (cpu6-cpu11). The surviving cluster is re-added in the cpu-map as cluster0, since the kernel stops scanning at the first missing clusterN index. cpu6-cpu11 are reassigned to SCMI performance domain 0, as domain 1 is no longer present. Kalambo uses PDP1 for SCMI transport. The tx shmem (lpri1) sits at offset 0x200 within imem, pushing the tx region end to 0x380, so the imem size is overridden accordingly. The rx shmem (lpri0) remains at offset 0x0. The PDP mailbox registers are overridden to match the Kalambo SCP firmware. Kalambo's PDC input mux differs from Glymur. Pins 109 and 110 carry tsens6 and tsens7 alarms, which are absent on Kalambo, and pins 134, 138, 156, 158, 172, 181 and 202 carry gp_irq_hvm inputs with nothing wired to them instead of wakeup GPIOs. Override the PDC ranges to leave those pins unmapped. Add labels to the cpus and cpu-map nodes in glymur.dtsi to allow derived SoCs to delete and redefine the cpu-map entirely. Link: https://lore.kernel.org/all/20260810-b4-kalambo-crd-v6-2-744e8ad1dae9@oss.qualcomm.com/ Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Co-developed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Introduce support for the CRD based on the Qualcomm Kalambo SoC. Similar to Mahua, it is pin-to-pin compatible with the Glymur CRD. It reuses the common CRD board description and drops the PMIC nodes not present on this design. Kalambo uses the same QREF topology as Mahua through the qcom,mahua-tcsr compatible TCSR block. Connect the QREF and refgen supply inputs to the corresponding CRD LDOs so that the reference clocks for the PCIe and USB PHYs can operate. Link: https://lore.kernel.org/r/20260810-b4-kalambo-crd-v6-3-744e8ad1dae9@oss.qualcomm.com Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
This reverts commit aba48bf. The patch got reverted because it's not match with the upstream patch.
Embedded Trace Router(ETR) is working as a DDR memory sink to collect tracing data from source device and the CTCU device serves as the control unit for the ETR device. Link: https://lore.kernel.org/all/20260714-add-ctcu-etr-for-glymur-v1-1-791de63c0713@oss.qualcomm.com/ Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
The OS PDC DRV register window on eliza spans 0x10000 bytes. Reduce the size of the first reg entry from 0x40000 to 0x10000. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260527094333.2311731-25-mukesh.ojha@oss.qualcomm.com Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
The Eliza CQS (CQ7790S) System-on-Module is designed to be connected to an Eliza EVK base board. The SoM provides the SoC, PMICs, LPDDR and eMMC, while the EVK base board provides connectors for a multitude of peripherals. Add the Eliza CQS SoM DTSI so it can be included by the EVK board DTS. Describe the regulators and board clocks, enable eMMC support through SDHC1, specify the ADSP firmware and enable the ADSP remoteproc. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260630-eliza-dts-qcs-evk-v4-2-18cbbdba6e7e@oss.qualcomm.com
The Eliza CQS EVK board combines the CQ7790S-based (Eliza) SoM with the common Eliza EVK base board, which provides connectors for different peripherals. Add a common Eliza EVK dtsi for the base board bits that can be reused alongside other Eliza SoM variants. Then, add the final Eliza CQS EVK dts, including the CQS SoM and common EVK dtsi. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260630-eliza-dts-qcs-evk-v4-3-18cbbdba6e7e@oss.qualcomm.com
# Conflicts: # arch/arm64/boot/dts/qcom/Makefile
…emory and SMMU mappings" This change have introduced an issue on multimedia builds where AudioRecord is broken on monaco-evk board. [ 153.325884] q6apm-lpass-dais 3000000.remoteproc:glink-edge:gpr:service@1:bedais: Failed to start APM port 19 [ 153.335982] q6apm-lpass-dais 3000000.remoteproc:glink-edge:gpr:service@1:bedais: ASoC error (-110): at soc_dai_trigger() on SEC_MI2S_TX [ 153.348489] MultiMedia2 Capture: ASoC error (-110): at dpcm_be_dai_trigger() on MultiMedia2 Capture [ 153.357875] MultiMedia2 Capture: ASoC error (-110): trigger FE cmd: 1 failed Revert the change for now, to fix the issue. This reverts commit cd0f5c6. Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
…emory and SMMU mappings" This change have introduced an issue on multimedia builds where AudioRecord is broken on lemans-evk board. [ 840.168044] q6apm-lpass-dais 30000000.remoteproc:glink-edge:gpr:service@1:bedais: Failed to start APM port 21 [ 840.178229] q6apm-lpass-dais 30000000.remoteproc:glink-edge:gpr:service@1:bedais: ASoC error (-110): at soc_dai_trigger() on TERT_MI2S_TX [ 840.190901] MultiMedia2 Capture: ASoC error (-110): at dpcm_be_dai_trigger() on MultiMedia2 Capture [ 840.200277] MultiMedia2 Capture: ASoC error (-110): trigger FE cmd: 1 failed Revert the change for now, to fix the issue. This reverts commit f75b90a.
This change have introduced a regression on Shikra board, wherein Rx on UART Shell is stuck, and no input is accepted. Issue: qualcomm-linux#921 Revert the change for now, to fix the issue. This reverts commit 6a36c4b. Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
… EVK" Compilation breaking with this change, so revert for now. This reverts commit 8c9d598. Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
Compilation breaking with this change, so revert for now. This reverts commit 9455e01. Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
…nchors to board file of_graph_is_present() only checks for the presence of a 'port' child node, not whether remote-endpoint is actually connected. Adding empty port anchor nodes to monaco.dtsi caused hci_qca to enter the M.2 pwrseq probe path on all monaco-based boards, including qcs8300-ride which has a soldered WCN6855 and no M.2 Key E connector. This broke BT initialization on qcs8300-ride. Fix this by moving the port/endpoint nodes from monaco.dtsi into the monaco-evk.dts board file where the M.2 connector is actually present, so that of_graph_is_present() only returns true for boards that have an M.2 Key E connector described. Fixes: 2479c6b ("FROMLIST: arm64: dts: qcom: monaco: Add graph port/endpoint anchors to pcieport0 and uart2") Link: https://lore.kernel.org/all/20260819-b4-monaco-evk-m2-v1-v3-4-988145ef65cd@oss.qualcomm.com/ Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com>
…gulator" This reverts commit 32998bb in favour of the upstream fix, which is applied in the following patch. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
…CIe PHYs The QMP PCIe PHYs on QCS8300 require dedicated qref and refgen voltage supplies for stable operation. Without these supplies, the system may occasionally crash. Add vdda-qref-supply and vdda-refgen-supply in the board files (QCS8300-RIDE, Monaco-EVK and Monaco-Monza-SoM), and add refgen-supply in the SoC DTSI (monaco.dtsi) since refgen is an on-chip regulator shared across boards. The PHY driver votes for refgen3 directly as a workaround for a hardware issue where QREF actually depends on refgen3 rather than refgen2 as documented. Link: https://lore.kernel.org/all/20260810112735.1326807-4-ziyue.zhang@oss.qualcomm.com/ Fixes: 33967ea ("arm64: dts: qcom: qcs8300-ride: enable pcie0 interface") Fixes: cdb613a ("arm64: dts: qcom: qcs8300-ride: enable pcie1 interface") Fixes: 41e2424 ("arm64: dts: qcom: monaco-evk: Enable PCIe0 and PCIe1.") Fixes: 5238f4e ("arm64: dts: qcom: Add Monaco Monza SoM") Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
…ault"" The kaanapali-MTP crash that prompted the workaround was due to frame done timeouts on DSI. That issue is now fixed and frame done timeouts are no longer seen on kaanapali DSI with virtual planes enabled. Virtual planes are also required for 4K display support on Kodiak (SC7280). Re-enable virtual planes by default. This reverts commit 7a17c61. Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
Adding merge log file and topic_SHA1 file Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
…pub/scm/linux/kernel/git/torvalds/linux.git tech/bsp/clk 24b9b5e 32 tech/bsp/devfreq 4809534 7 tech/security/firmware-smc de7413c 6 tech/bsp/soc-infra ff6ff7b 22 tech/bsp/pinctrl 79149ef 1 tech/bsp/remoteproc 39a86aa 13 tech/bus/peripherals e6f6741 8 tech/bus/pci/all 99d5cf2 45 tech/bus/pci/phy 66e44c2 14 tech/bus/usb/dwc d90fb64 4 tech/bus/usb/phy c3aa7d5 35 tech/debug/hwtracing a3f730f 24 tech/pmic/misc 8d60b51 22 tech/mem/iommu cdc9e80 9 tech/mm/audio/all 88b8f29 8 tech/mm/camss dffc6e9 49 tech/mm/drm 83f65e1 76 tech/mm/fastrpc bff2f47 12 tech/mm/video bdcc5c4 127 tech/mm/gpu b9f2291 12 tech/mproc/rpmsg 55dc464 1 tech/net/ath 2ac1acc 21 tech/net/bluetooth 450dc5e 7 tech/pm/power f712532 16 tech/pm/thermal d525ff9 8 tech/security/crypto 1f60c0a 23 tech/security/ice beabac0 9 tech/storage/all cef1b3c 5 tech/all/dt/qcs6490 2e92fd1 28 tech/all/dt/qcs9100 754b808 24 tech/all/dt/qcs8300 a02cf61 31 tech/all/dt/qcs615 66b7e2f 11 tech/all/dt/agatti 2ca1b63 2 tech/all/dt/eliza 5338032 25 tech/all/dt/hamoa 106f486 49 tech/all/dt/glymur c5bf216 60 tech/all/dt/kaanapali d21ef73 26 tech/all/dt/pakala 450d786 9 tech/all/config 7b48e6e 78 tech/overlay/dt b895d0e 78 tech/all/workaround 219d869 12 tech/mproc/all 104969c 2 tech/noup/debug/all e473076 29 tech/hwe/unoq a2d85fe 4 early/hwe/shikra/drivers b19d2ec 184 early/hwe/shikra/dt dd90d88 130 early/hwe/lyra 8c9d598 6
Qcom platforms has the legacy of using non-standard SCM calls splintered over the various kernel drivers. These SCM calls aren't compliant with the standard SMC calling conventions which is a prerequisite to enable migration to the FF-A specifications from Arm. OP-TEE as an alternative trusted OS to Qualcomm TEE (QTEE) can't support these non-standard SCM calls. And even for newer architectures using S-EL2 with Hafnium support, QTEE won't be able to support SCM calls either with FF-A requirements coming in. And with both OP-TEE and QTEE drivers well integrated in the TEE subsystem, it makes further sense to reuse the TEE bus client drivers infrastructure. The added benefit of TEE bus infrastructure is that there is support for discoverable/enumerable services. With that client drivers don't have to manually invoke a special SCM call to know the service status. So enable the generic Peripheral Authentication Service (PAS) provided by the firmware. It acts as the common layer with different TZ backends plugged in whether it's an SCM implementation or a proper TEE bus based PAS service implementation. Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260427095603.1157963-5-sumit.garg@kernel.org/
With the availability of generic PAS service, let's add SCM calls as a backend to keep supporting legacy QTEE interfaces. The exported qcom_scm* wrappers will get dropped once all the client drivers get migrated as part of future patches. Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260427095603.1157963-5-sumit.garg@kernel.org/
Add support for Peripheral Authentication Service (PAS) driver based on TEE bus with OP-TEE providing the backend PAS service implementation. The TEE PAS service ABI is designed to be extensible with additional API as PTA_QCOM_PAS_CAPABILITIES. This allows to accommodate any future extensions of the PAS service needed while still maintaining backwards compatibility. Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260427095603.1157963-5-sumit.garg@kernel.org/
Switch qcom_q6v5_pas client driver over to generic PAS TZ APIs. Generic PAS TZ service allows to support multiple TZ implementation backends like QTEE based SCM PAS service, OP-TEE based PAS service and any further future TZ backend service. Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260427095603.1157963-5-sumit.garg@kernel.org/
Switch qcom_q6v5_mss client driver over to generic PAS TZ APIs. Generic PAS TZ service allows to support multiple TZ implementation backends like QTEE based SCM PAS service, OP-TEE based PAS service and any further future TZ backend service. Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260427095603.1157963-5-sumit.garg@kernel.org/
Switch mdtloader client driver over to generic PAS TZ APIs. Generic PAS TZ service allows to support multiple TZ implementation backends like QTEE based SCM PAS service, OP-TEE based PAS service and any further future TZ backend service. Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260427095603.1157963-5-sumit.garg@kernel.org/
Switch qcom_wcnss client driver over to generic PAS TZ APIs. Generic PAS TZ service allows to support multiple TZ implementation backends like QTEE based SCM PAS service, OP-TEE based PAS service and any further future TZ backend service. Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260427095603.1157963-5-sumit.garg@kernel.org/
Select PAS generic service driver to enable support for multiple PAS backends like OP-TEE in addition to SCM. Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260427095603.1157963-5-sumit.garg@kernel.org/
Switch drm/msm client drivers over to generic PAS TZ APIs. Generic PAS TZ service allows to support multiple TZ implementation backends like QTEE based SCM PAS service, OP-TEE based PAS service and any further future TZ backend service. Acked-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260427095603.1157963-5-sumit.garg@kernel.org/
Switch qcom media client drivers over to generic PAS TZ APIs. Generic PAS TZ service allows to support multiple TZ implementation backends like QTEE based SCM PAS service, OP-TEE based PAS service and any further future TZ backend service. Along with that pass proper PAS ID to set_remote_state API. As per testing the SCM backend just ignores it while OP-TEE makes use of it to for proper book keeping purpose. Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260427095603.1157963-5-sumit.garg@kernel.org/
Switch ipa client driver over to generic PAS TZ APIs. Generic PAS TZ service allows to support multiple TZ implementation backends like QTEE based SCM PAS service, OP-TEE based PAS service and any further future TZ backend service. Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260427095603.1157963-5-sumit.garg@kernel.org/
Switch ath12k client driver over to generic PAS TZ APIs. Generic PAS TZ service allows to support multiple TZ implementation backends like QTEE based SCM PAS service, OP-TEE based PAS service and any further future TZ backend service. Acked-by: Jeff Johnson <jjohnson@kernel.org> Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260427095603.1157963-5-sumit.garg@kernel.org/
Now since all the Qcom SCM client drivers have been migrated over to generic PAS TZ service, let's drop the exported SCM PAS wrappers. Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260427095603.1157963-5-sumit.garg@kernel.org/
Add Sumit Garg as the maintainer for the Qualcomm generic Peripheral Authentication Service (PAS) as well as the PAS TEE backend driver. Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260427095603.1157963-5-sumit.garg@kernel.org/
qcom_scm_mem_protect_video_var() is not serviced when PAS is backed by OP-TEE (the TEE owns secure memory protection), so its failure there is expected. Add qcom_pas_is_tee_backed() to report when the active PAS backend is the OP-TEE one, and in iris only treat the SCM failure as fatal when OP-TEE is not on the bus. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
Test Matrix
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Salendarsingh Gaud (sgaud-quic)
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Optee changes on top of kernel v7.2