monaco-evk: Enable PCIe M.2 Key E connector - #893
monaco-evk: Enable PCIe M.2 Key E connector#893weiden (WeiDeng-weiden) wants to merge 4 commits into
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…etooth support" This reverts commit ba34902. Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com>
Add 'compatible = "pciclass,0604"' to the pcieport0 node in monaco.dtsi to allow the PCI subsystem to associate the DT node with the PCI-to-PCI bridge device. This is required for downstream DT nodes (such as M.2 connectors described as graph endpoints of the Root Port) to be matched to PCI devices. Link: https://lore.kernel.org/r/20260729-b4-monaco-evk-m2-v1-v2-1-0548e1dab760@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com>
…o pcieport0 and uart2 Add empty graph port/endpoint nodes to pcieport0 and uart2 in monaco.dtsi so that board files can reference the endpoint labels (pcieport0_ep, uart2_ep) to describe connections to M.2 Key E connectors via remote-endpoint overrides. Link: https://lore.kernel.org/r/20260729-b4-monaco-evk-m2-v1-v2-2-0548e1dab760@oss.qualcomm.com/ Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com>
…onnector The monaco EVK has a PCIe M.2 Mechanical Key E connector to connect wireless connectivity cards over PCIe and UART interfaces. Hence, describe the connector node and link it with the PCIe 0 Root Port and UART2 nodes through graph port/endpoint. The M.2 Key E connector is powered by a 3.3V fixed regulator (vreg_wcn_3p3) which is sourced from the board's 12V DC input rail (vreg_dcin_12v). Both regulators are always-on and are required by the pcie-m2-e-connector binding. Also add the serial1 = &uart2 alias, which is required for the Bluetooth serdev device to be enumerated on the UART2 interface. The graph endpoint anchors (pcieport0_ep, uart2_ep) referenced here are defined in monaco.dtsi (see "arm64: dts: qcom: monaco: Add graph port/endpoint anchors to pcieport0 and uart2"). Link: https://lore.kernel.org/r/20260729-b4-monaco-evk-m2-v1-v2-3-0548e1dab760@oss.qualcomm.com/ Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com>
PR #893 — validate-patchPR: #893
Final Summary
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PR #893 — checker-log-analyzerPR: #893
Detailed report: Full report
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Adapted for vendor tree: applied to monaco-evk.dts after reverting the Bluetooth workaround from monaco-evk-common.dtsi. |
Enabling the PCIe M.2 Key E connector on Monaco EVK
and reverting the temporary Bluetooth workaround.
Revert BT workaround:
regulators to work around the missing M.2 binding. Now superseded by
the proper M.2 solution.
monaco.dtsi:
compatible = "pciclass,0604"to the PCIe Root Port node, requiredfor
pci_pwrctrlto associate the DT node with the PCI-to-PCI bridgepcieport0_ep,uart2_ep) so boardfiles can reference them via
remote-endpointmonaco-evk.dts:
graph endpoints, regulator properties (
vreg_wcn_3p3,vreg_dcin_12v)serial1 = &uart2alias required for Bluetooth serdev enumerationUpstream: https://lore.kernel.org/r/20260729-b4-monaco-evk-m2-v1-v2-0-0548e1dab760@oss.qualcomm.com/
CRs-Fixed: 4610036