Xqccmt extension v0.1.0

Xqccmt v0.1.0 — Qualcomm Custom Compressed Jump Table Extension

Xqccmt is a Qualcomm custom variant of the standard RISC-V Zcmt (Compressed Jump Table) extension, designed for the qc_iu microcontroller configuration.

Overview

Xqccmt reuses the always-zero bit 0 of call table entries (pointed to by the jvt CSR) as metadata to select the return address register:

• Bit 0 = 0 — save return address in ra (x1), identical to standard cm.jalt behavior
• Bit 0 = 1 — save return address in t0 (x5), Qualcomm alternative link register
• Jump target is always {entry[XLEN-1:1], 1'b0} (bit 0 masked out)

Instructions

Mnemonic	Equivalent	Description
qc.cm.jt	cm.jt	Compressed jump via table (index 0–31), identical behavior
qc.cm.jalt	cm.jalt	Compressed jump-and-link via table (index 32–255), with ra/t0 selection

Notes

• Xqccmt and Zcmt use identical encodings and are mutually exclusive — they cannot coexist in the same configuration
• Requires Zca >= 1.0.0
• Targets the qc_iu (32-bit) microcontroller configuration

Contributors

• Albert Yosher, Qualcomm Technologies, Inc.
• Derek Hower, Qualcomm Technologies, Inc.

Xqccmi extension v0.2.0

Xqccmi v0.2.0 — Qualcomm Custom Compressed Instruction Lookup Table Extension

First public release of Xqccmi, incorporating all changes from v0.1.0 and v0.2.0.

Overview

Xqccmi introduces a custom instruction lookup table (ILUT) mechanism for the qc_iu microcontroller configuration. Each ILUT entry is a 64-bit double entry that packs
two sub-instructions, supporting 16-bit, 32-bit, and 48-bit instructions. Two new CSRs are introduced: qc.itba (ILUT base address) and qc.itdec (ILUT decode control).

Instructions

Mnemonic	Description
qc.cm.ilut	Execute a dual-instruction ILUT entry indexed via qc.itba and qc.itdec

Trap Semantics & Resume Mechanism

• Each sub-instruction within a qc.cm.ilut entry can trap independently; traps are taken immediately at the faulting sub-instruction
• Bit 0 of mepc/mnepc encodes which sub-instruction caused the trap (0 = first, 1 = second)
• On trap return, qc.cm.ilut re-enters with PC bit 0 reflecting this value; if set, the first sub-instruction is skipped
• Bit 0 of mepc/mnepc is readable and writable — software may set it to 1 to force resumption from the second sub-instruction

Instruction Restrictions

The following instruction categories are forbidden inside an ILUT entry:

• PC-relative instructions
• Register-indirect jumps: jalr, c.jr, c.jalr
• Return instructions: cm.popret, cm.popretz, qc.cm.popret, qc.cm.popretz

Requirements

• Zca >= 1.0.0
• Zicsr >= 2.0.0
• Mutually exclusive with Zcd

Contributors

• Albert Yosher, Qualcomm Technologies, Inc.
• Derek Hower, Qualcomm Technologies, Inc.
• Gil Zukerman, Qualcomm Technologies, Inc.

Xqci extension v0.13

Full Changelog: Xqci-0.12.0...Xqci-0.13.0
changes:
- Fix version history of releases v0.11.0 and v0.12.0
- Fix description and IDL code of qc.csrrwr instruction to allow just read CSR
- Fix IDL code of qc.c.mileaveret instruction to avoid restoring from stack NMIP and EXCP bits

Xqci extension v0.12

changes:
- Fix desciption of qc.c.eir instruction to match IDL code and functionality
- Fix encoding of qc.swm and qc.swmi instructions to state that rs3 cannot be x0
- Fix description and IDL code of qc.swm and qc.lwm instructions to state that length is in rs2[4:0]

Xqci extension v0.11

changes:
- Fix IDL code of qc.shlusat instruction (should use zero-extension and not sign-extension)
- Fix IDL code of qc.shlusat and qc.shlsat instructions (should compare values of xlen()*2 bits)
- Fix IDL code of qc.shlusat and qc.shlsat instructions because change in IDL operators (width adjustment)
- Fix IDL code of qc.subsat, qc.addusat and qc.addsat instructions because change in IDL operators (width adjustment)
- Fix IDL code for qc.c.mileaveret, qc.c.mnret and qc.c.mret instructions because change in IDL '<<' operator
- Fix IDL code for qc.c.clrint, qc.c.setint, qc.clrinti and qc.setinti instructions because change in IDL '<<' operator
- Fix IDL code for qc.c.di, qc.c.dir, qc.c.ei, qc.c.eir and qc.c.mienter.nest instructions because change in IDL '<<' operator
- Fix IDL code for qc.c.sync, qc.c.syncr, qc.c.syncwf and qc.c.syncwl instructions because change in IDL '<<' operator
- Fix IDL code for qc.c.bseti, qc.c.extu, qc.ext and qc.extu instructions because change in IDL '<<' operator
- Fix IDL code for qc.extd, qc.extdu, qc.extdr and qc.extdur instructions because change in IDL '<<' operator
- Fix IDL code for qc.extdpr, qc.extdprh, qc.extdupr and qc.extduprh instructions because change in IDL '<<' operator
- Fix IDL code for qc.insb, qc.insbi, qc.insbr and qc.insbri instructions because change in IDL '<<' operator
- Fix IDL code for qc.insbh, qc.insbhr, qc.insbpr and qc.insbprh instructions because change in IDL '<<' operator

Xqci extension v0.10

changes:
- Fix IDL code for Smdbltrp and Smrnmi spec compatibility for qc.c.mileaveret instruction

Xqci extension v0.9

changes:
- Fix IDL code sign extension logic for qc.e.lb and qc.e.lh instructions
- Fix IDL code sign extension logic for qc.ext and qc.extd instructions
- Fix IDL code sign extension logic for qc.extdpr, qc.extdprh and qc.extdr instructions
- Fix IDL code and description increasing shift to 6 bit for qc.extdr and qc.extdur instructions
- Fix IDL code and description increasing shift to 6 bit for qc.extdpr and qc.extdprh instructions
- Fix IDL code and description increasing shift to 6 bit for qc.extdupr and qc.extduprh instructions
- Fix IDL code sign extension logic for qc.lieq instruction
- Fix wrong mantissa bit selection in qc.norm, qc.normu and qc.normeu instructions
- Fix wrong exponent calculation in qc.normeu instruction
- Fix IDL code and description of qc.setwm instruction to state that number of words written 0..31.
- Fix IDL code for Smdbltrp and Smrnmi spec compatibility for qc.c.mret and qc.c.mnret instructions

Xqci extension v0.8

- Fix rs1 cannot be 31 for qc.extdu, qc.extd, qc.extdur, instructions
- Fix rs1 cannot be 31 for qc.extduprh, qc.extdprh, qc.extdupr, qc.extdr qc.extdpr instructions
- Fix typos in IDL code (missing ')' ) for qc.extdpr, qc.extdr instructions
- Fix IDL code and description to look correct in PDF for qc.insbhr and qc.insbh instructions
- Fix Xqci extension description to reflect correct 48-bit format field names
- Fix IDL code to to match description for qc.insbr instruction
- Add stack checks to qc.c.mienter, qc.c.mienter.nest, qc.c.mileaveret

Xqccmp_extension-0.3.0

- Fix all push and pop instructions IDL code to take in consideration that xlen() returns bits and not bytes
- Declare state of extension as "frozen"

Xqci extension v0.7

Xqci Extension verion 0.7 changes:
- Fix typos in description of qc.shlsat and qc.shlusat instructions
- Fix bug in qc.shlsat that caused wrong IDL code result
- Fix clobbering of saturation results in [add|addu|sub]sat instructions
- Rename all custom CSRs of the Xqciint extension to use dot as separator in the name
- Fix addresses of qc.mclicie* CSRs to 0x7f8-0x7ff (was copy & paste from qc.mclicip*)
- Add missing CSR registers qc.mclicilvl00 - qc.mclicilvl31
- Add missing CSR registers qc.mwpstartaddr0 - qc.mwpstartaddr3 and qc.mwpendaddr0 - qc.mwpendaddr3
- Add missing CSR registers qc.mstkbottomaddr and qc.mstktopaddr
- Add missing CSR registers qc.mmcr, qc.mthreadptr, qc.mcause
- Remove CSR registers qc.mncause, qc.mnepc
- Fix IDL code for qc.c.mienter, qc.c.mienter.nest, qc.c.mileaveret, qc.c.mret, qc.c.mnret
- Add list of supported custom exceptions
- Fix qc.cto instruction IDL code
- Change width calculations for qc.extdpr, qc.extdprh, qc.extdr, qc.extdupr, qc.extduprh, qc.extdur,
- Change width calculations for qc.insbhr, qc.insbpr, qc.insbprh, qc.insbr, qc.insbri