Schematic file format

[GeneralAccess]

I’m updating a utility that uses .sch and .sim files to make a netlist file to import into stripboard design tools.

I was getting the components from the .sch schematic file and the connections from the .sim simulation output file, but I think I can use the sch file for both. Is that so and is it in the section, or do I need some sort of link with the section too?

In this partial Wires section with my asterixes:

<140 520 220 520 "" 0 0 0 ""> netA netB
<140 310 140 520 "" 0 0 0 ""> ---- netA
<-10 520 140 520 "" 0 0 0 ""> ---- netA
<220 520 280 520 "" 0 0 0 ""> netB ----

I think each pair of numbers is a location.
They nearly match the location of one end of a component, how can I decide what counrs as a connection? There is no match for the other end, is that worked out by knowing the length of the component?

I can't find anything in the otherwise comprehensive documentation.

[GeneralAccess]

I might try the .cir or .cdt files instead.

[ra3xdh]

Qucs-S doesn't produce files with *.sim extension. What exactly software are you using? The XML format of the schematic file is described here: https://qucs-help.readthedocs.io/en/latest/internal.html#schematic-file-format The section Wires is the same for Qucs and Qucs-S.

The CIR file is SPICE netlist. It doesn't contain information about schematic wires geometry and components placement. The RefDes for some devices may be changed because of SPICE requirements. Some devices may be represented by SPICE equivalent circuit. Refer to Ngspice manual for CIR netlist syntax.

[GeneralAccess]

"Qucs-S doesn't produce files with *.sim extension."
Qucs-s -n -i example2.sch -o example2.sim
My choice of extension.

Doc says .sch file "Shows the centre of the component" That explains why the wire ends don't meet the tags. I would need to know a lot about each component to be able to work out the connections from this file, so it's not practical. The .CDR format looks simpler than the .CIR file, but there is no mention of the four ICs in my example circuit, so if the .CIR file would be better
I would interpret the first line
R8 _net0 _net1 ....
as
component-name, first tag connection, second tag connection, ....irrelevant
It doesn't matter with a resistor, but with a capacitor for example, I's need to know a rule like "the positive connection is always the first".

Then
B_OP1 _net12 0 V = 1E6V(_net7,_net5)u(15-1E6V(_net7,_net5))u(1E6V(_net7,_net5)-(-15))+15u(1E6*V(_net7,_net5)-15)+(-15)u((-15)-1E6V(_net7,_net5))
component-name, ?output connection, (_net7, _net5) as +ve output, -ve output or vice-versa.

.CIR-------------------
R8 _net0 _net1 50 tc1=0.0 tc2=0.0
L1 _net2 _net3 1N
XD4 0 _net4 _net1 Z_Diodes_BZT52C10T
B_OP4 _net5 0 V = 1E6V(_net4,_net0)u(15-1E6V(_net4,_net0))u(1E6V(_net4,_net0)-(-15))+15u(1E6V(_net4,_net0)-15)+(-15)u((-15)-1E6V(_net4,_net0))
XD3 0 _net1 _net6 LEDs_red
R4 _net7 _net3 50 tc1=0.0 tc2=0.0
R9 _net5 _net4 50 tc1=0.0 tc2=0.0
XD2 0 _net1 _net8 LEDs_yellow
V1 _net2 _net1 DC 12
C1 _net1 _net3 100N
R5 _net1 _net7 50 tc1=0.0 tc2=0.0
XD1 0 _net1 _net9 LEDs_green
R2 _net10 _net8 1000 tc1=0.0 tc2=0.0
R3 _net11 _net6 2200 tc1=0.0 tc2=0.0
R10 _net3 _net4 1000000 tc1=0.0 tc2=0.0
B_OP1 _net12 0 V = 1E6V(_net7,_net5)u(15-1E6V(_net7,_net5))u(1E6V(_net7,_net5)-(-15))+15u(1E6V(_net7,_net5)-15)+(-15)u((-15)-1E6V(_net7,_net5))
B_OP2 _net10 0 V = 1E6V(_net7,_net13)u(15-1E6V(_net7,_net13))u(1E6V(_net7,_net13)-(-15))+15u(1E6V(_net7,_net13)-15)+(-15)u((-15)-1E6V(_net7,_net13))
B_OP5 _net11 0 V = 1E6V(_net7,_net0)u(15-1E6V(_net7,_net0))u(1E6V(_net7,_net0)-(-15))+15u(1E6V(_net7,_net0)-15)+(-15)u((-15)-1E6V(_net7,_net0))
R6 _net5 _net13 50 tc1=0.0 tc2=0.0
R7 _net0 _net13 50 tc1=0.0 tc2=0.0
R1 _net9 _net12 1000 tc1=0.0 tc2=0.0

.control

CDR--------------------
.GLOBAL 0:G
R8 _net0 _net1 50
L1 _net2 _net3 1N
XD4 0 _net4 _net1 Z_Diodes_BZT52C10T

XD3 0 _net1 _net6 LEDs_red
R4 _net7 _net3 50
R9 _net5 _net4 50
XD2 0 _net1 _net8 LEDs_yellow
V1 _net2 _net1 12
C1 _net1 _net3 100N
R5 _net1 _net7 50
XD1 0 _net1 _net9 LEDs_green
R2 _net10 _net8 1000
R3 _net11 _net6 2200
R10 _net3 _net4 1000000

R6 _net5 _net13 50
R7 _net0 _net13 50
R1 _net9 _net12 1000
.END

My output is quite simple, it's for input to DIY Layout Creator (for Veroboard/stripboards). It looks like this.
[
R7
RESISTOR
50 Ohm

]
...
(
_net0
R8-1
OP4-1
OP5-1
R7-1
)
...

Qucs-s is the best Linux tool I've found for schematic design and DIYLC is great for stripboard design. I may consider producing input/output modules for other combinations in the future, as schematic design tools may include PCB design, but they don't do stripboard design.

[GeneralAccess]

I put too much irrelevant information in my previous post, but it's not possible to edit it now.

To sum up:
-Relying on the format of 2 files staying the same isn't ideal.
-The schematic file doesn't contain net data in a usable format.
-I don't think the .cir file does either
-The .cdl file does.
-Having to use a command line statement to run the program to produce a .sim file isn't ideal, but neither is asking the user to output a CDL file.

If it was possible to produce the the .cdl file with a command line statement, it would be worth changing to using that.

I'll stick with using using the schematic for components and the simulation file for nets. If something changes I'll reconsider that.