Computer Design and Prototyping project where I designed a multicore 5 stage pipelined processor with L1 cache implementation. The MSI coherence protocol is also implemented to take care of coherency issues. It is based on the MIPS instruction set architecture.
Processor designs currently completed and fully functioning :-
- [Endpoint coverage](#progress) Single Cycle Processor Design
- [Endpoint coverage](#progress) Pipelined Processor Design without Branch Prediction
- [Endpoint coverage](#progress) Pipelined Processor Design with Branch Prediction
- [Endpoint coverage](#progress) Pipelined Processor Design with Branch Prediction and an L1 instruction cache and data cache
- [Endpoint coverage](#progress) Multicore processor Design with each core being Pipelined along with Branch Prediction and an L1 instruction cache and data cache along with a memory bus controller that implements the MSI protocol