Reproduce and resolve gfx1151 EngineCore model-load segfault

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Objective

Reproduce and resolve the gfx1151 EngineCore libhsa-runtime64.so model-load segfault using a coherent supported ROCm stack.

Target hardware

• AMD Strix Halo / RDNA 3.5 / gfx1151

References

• [Bug]: [ROCm][gfx1151] Engine Core segfaults in libhsa-runtime64.so when loading Qwen3-VL-32B-AWQ on AMD Ryzen AI MAX+ 395 vllm-project/vllm#37151
• Related fork issue: Evaluate official-release ROCm gfx1151 image path for Strix Halo #4
• Upstream APU memory reporting: fix(rocm): detect AMD APU and fix VRAM reporting for unified memory vllm-project/vllm#40963

Context

The fork already has equivalent integrated-GPU memory reporting, so this issue excludes that work. Focus is the hard model-load crash and whether it belongs to vLLM, torch, ROCm/HSA runtime, or an incoherent package mix.

Proposed work

• Reproduce on the fork's coherent gfx1151 ROCm SDK/Torch environment.
• Capture native backtrace, ROCm/HSA versions, loaded shared libraries, and the smallest model/config that crashes.
• Differential-test known coherent release/nightly stacks and a direct torch allocation/load reproducer.
• Fix vLLM only if evidence reaches a vLLM code path; otherwise produce an actionable upstream ROCm/torch report and pin the known-good stack.

Acceptance criteria

• Minimal deterministic reproducer and symbolized crash evidence exist.
• Root cause is assigned to the correct layer.
• On the minimized model/config, EngineCore loads and returns the expected deterministic tokens without CPU fallback or segfault.
• Peak unified memory, TTFT, and decode throughput are reported for later qualification.