SOC_design

DAY 1

Introducation to QFN-48 and also Introduction to Openlane and familiarization with it
The microcontroller usually consists of the core alongwith storage elements, IPs, PLLs, DAC and ADC and other peripherals. An SOC is an integrated chip with all components and peripherals on the same die. It also needs an OS. The OS is responsible for allocating memorty and to handle I/O operations. This acts as an interface between software to hardware. The compiler converts the high-level language to lower level assembly language. This code is then converted to computer binary format(1/0s) by the assembler. Based on the computer instrusction set, the compiler converts to assembly language. And here, RISCV is an open source instruction set architecture and its specialilty is, it is open-source. Meaning it is open to customization. Later, Hardware descriptive lnaguages like Verilog is used to draw the logic onto the hardware. The RTL defines the flow of data between registers and the logical operations performed. Finally, the netlist genenarated from synthesis are placed and routed onto the silicon die.

Openlane is an open source tool for ASIC design with open RTL designs, open EDA tools and open PDKs. It is benefical for users like us who are into experiments during education or worksshops. This tool allows for complete RTL2GDS flow. RTL Synthesis Floorplanning & Placement CTS & Routing: Static Timing Analysis (STA) Physical Verification DFT(Design for Test) Static Timing analysis(STA)violations is there Physical Verification(DRC and LVS)

Design Preparation Running commands: docker

./flow.tcl -interactive

package require openlane 0.9 prep -design picorv32a

run_synthesis

Flop ratio = no of ff / no of cells = 1613/14876 = 0.108 = 10.8%

DAY2

Open the layout after placement type the command magic -T home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read
picorv32a.placement.def & After Placement