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@renesas-rz-fsp-development renesas-rz-fsp-development released this 28 Jul 08:59
v4.2.0
5d78050

Release Notes

Flexible Software Package (FSP) for Renesas RZ, version 4.2.0.

Download the FSP with e2 studio Installer for this release, setup_rzfsp_v4_2_0_e2s_v2026-07.exe, from here.

If using IAR Embedded Workbench for Arm, download the FSP Smart Configurator for this release, setup_rzfsp_v4_2_0_rzsc_v2026-07.exe, from here.

All installers are available in the Assets section of this release.

Refer to the README.md in the FSP root folder for setup instructions, hardware details, and related links.

Tools

New Features

  • RZ/A series
    • Updated LVGL graphic library to version v9.5.
    • Added support for USB HCDC.
    • r_mtu3
      • The MTIOCnC and MTIOCnD function support added to Timer, Multi-Function (r_mtu3).
      • Added a Compare Match B configuration option to the configuration menu to Timer, Multi-Function (r_mtu3).
        When Counter Clear Source is set to Disabled, compare match events for TGRA and TGRB can be configured using the Compare Match and Compare Match B settings, respectively.
  • RZ/G series
    • Added support for RZ/G3L and RZ/G3SE devices.
    • r_mtu3
      • The MTIOCnC and MTIOCnD function support added to Timer, Multi-Function (r_mtu3).
      • Added a Compare Match B configuration option to the configuration menu to Timer, Multi-Function (r_mtu3).
        When Counter Clear Source is set to Disabled, compare match events for TGRA and TGRB can be configured using the Compare Match and Compare Match B settings, respectively.
    • Master receive clock configuration and analog/digital delay functions suppor added to SPI_B (r_spi_b).
  • RZ/N series
    • SCIE driver support added to UART(r_sci_uart, r_scie_uart).
    • r_mtu3
      • The MTIOCnC and MTIOCnD function support added to Timer, Multi-Function (r_mtu3).
      • Added a Compare Match B configuration option to the configuration menu to Timer, Multi-Function (r_mtu3).
        When Counter Clear Source is set to Disabled, compare match events for TGRA and TGRB can be configured using the Compare Match and Compare Match B settings, respectively.
  • RZ/T series
    • Ethernet Generic PTP Timer driver support added (r_gptp).
    • HSR/PRP Switch driver support added (r_hpsw).
    • Layer3 Ethernet Switch driver support added (r_layer3_switch).
    • NAND Flash driver support added (r_nandc).
    • Ethernet driver support added (r_rmac).
    • SCIE driver support added to UART(r_sci_uart, r_scie_uart).
    • r_mtu3
      • The MTIOCnC and MTIOCnD function support added to Timer, Multi-Function (r_mtu3).
      • Added a Compare Match B configuration option to the configuration menu to Timer, Multi-Function (r_mtu3).
        When Counter Clear Source is set to Disabled, compare match events for TGRA and TGRB can be configured using the Compare Match and Compare Match B settings, respectively.
  • RZ/V series
    • r_mtu3
      • The MTIOCnC and MTIOCnD function support added to Timer, Multi-Function (r_mtu3).
      • Added a Compare Match B configuration option to the configuration menu to Timer, Multi-Function (r_mtu3).
        When Counter Clear Source is set to Disabled, compare match events for TGRA and TGRB can be configured using the Compare Match and Compare Match B settings, respectively.
    • The R_PDM_SoundDetectionEnable and R_PDM_SoundDetectionDisable functions support added to PDM (r_pdm).
    • Master receive clock configuration and analog/digital delay functions suppor added to SPI_B (r_spi_b).

Third Party Software

These third party software solutions are included alongside FSP.

Deprecations

  • RZ/A series
    • None
  • RZ/G series
    • None
  • RZ/N series
    • None
  • RZ/T series
    • None
  • RZ/V series
    • None

Bug Fixes and Improvements

  • RZ/A series
    • Fixed an issue where clicking the information icon for a module in the Stacks tab did not always open the corresponding FSP Documentation.
    • bsp
      • Added board-related information to the Board Description and Board Details sections.
      • Adjusted the wait time in the Initial Program Loader (IPL) to ensure sufficient time for FSP program download.
    • lvgl
      • Fixed an issue that prevented LVGL stacks from being added to RZ/A3UL projects.
      • Fixed an issue where an error message was incorrectly displayed even when the Color Depth and LCDC Input Format settings were configured correctly.
    • r_canfd
      • Fix the use of the CAN FD global timer prescaler property for the Data module.
    • r_dmac
      • Fixed an issue that allowed CAN FD events not supported on RZ/A3M to be selected as an Activation Source.
    • r_gether
      • Fixed an issue where a build error occurred when Link Signal Change Flag was set to Used.
    • r_gtm
      • Fixed an issue where the count period was one count longer than the configured value.
    • r_ioport
      • Fixed an issue where a build error occurred when changing the Name property value from the Property menu.
      • Added a note regarding the arguments of R_IOPORT_PortDirectionSet() to the FSP Documentation.
    • r_lcdc
      • Fixed an issue that allowed unsupported values to be configured for Number of Buffers.
      • Fixed an issue where user applications could not reference the Color Keying Configuration structure definition when the Name property was changed from its default value (g_display0).
    • r_mtu3
      • Fixed an issue where invalid pin output configurations were not reported as errors in Periodic mode when the enabled output pin did not match the selected counter clear source.
      • Renamed the FSP Configuration property items "MTIOCnA Pin Function" and "MTIOCnB Pin Function" to "TGRA I/O Pin Setting" and "TGRB I/O Pin Setting", respectively.
      • Fixed an issue where the compare match event used to trigger an A/D conversion request occurred one count later than the configured value.
        As a result of this fix, after updating FSP in an existing project, the compare match event for the A/D conversion request will occur one count earlier than in previous versions.
        To maintain the same timing as before, increase the configured compare match value by one count.
      • Fixed an issue that allowed unsupported interrupt priority values to be configured.
      • Fixed an issue where no error was reported when A/D Converter Activation by TGRA Input Capture/Compare Match, which is not supported for Channel 8, was enabled.
    • r_riic_slave
      • Fixed an issue where the valid range of values that could be configured for Slave Address was incorrect.
    • r_sci_uart
      • Fixed an issue where unsupported pins could be selected as RTS pins on the RZ/A3M.
    • r_scif_uart
      • Fixed an issue that allowed unsupported values to be configured for Baud Rate.
    • r_ssi
      • Fixed an issue where no error was reported when a DMAC stack was added while DMAC Support was disabled.
    • r_usb_basic
      • Changed R_USB_Read() and R_USB_Write() to validate the data size even when parameter checking is disabled.
    • r_usb_hhid
      • Fixed the valid range of endpoint numbers that can be configured for a pipe.
    • r_usb_pcdc
      • Fixed the value of subclass in the Device Descriptor for Arm Windows.
    • rm_comms_usb_pcdc
      • Fixed an issue where parameter checking was not enabled after changing the configuration.
    • rm_lvgl_port
      • Fixed an issue where the Framebuffer Name setting could not be changed.
    • rm_netx_secure_crypto_sw_port
      • Fixed a build error issue caused by unnecessary header file inclusion in standalone mode.
    • rm_openh264
      • Fixed an issue that prevented rm_openh264 stacks from being added.
    • rm_threadx_port
      • Fixed an issue where FPU registers were not saved and restored properly during FIQ/IRQ handler execution.
  • RZ/G series
    • Fixed an issue where clicking the information icon for a module in the Stacks tab did not always open the corresponding FSP Documentation.
    • bsp
      • Added board-related information to the Board Description and Board Details sections.
    • r_i3c_b
      • Fixed incorrect addresses and register accesses for the DATBASm (m=1-7) and EXDATBAS registers.
      • Fixed the maximum device count and FIFO buffer depth.
      • Fixed an issue where transmitted data could contain data from a previous transmission.
    • r_gtm
      • Fixed an issue where the count period was one count longer than the configured value.
    • r_gpt
      • Fixed an issue where the compare match event used to trigger an A/D conversion request occurred one count later than the configured value.
        As a result of this fix, after updating FSP in an existing project, the compare match event for the A/D conversion request will occur one count earlier than in previous versions.
        To maintain the same timing as before, increase the configured compare match value by one count.
    • r_ioport
      • Fixed an issue where a build error occurred when changing the Name property value from the Property menu.
      • Added a note regarding the arguments of R_IOPORT_PortDirectionSet() to the FSP Documentation.
    • r_lcdc
      • Fixed an issue where user applications could not reference the Color Keying Configuration structure definition when the Name property was changed from its default value (g_display0).
    • r_mtu3
      • Fixed an issue where invalid pin output configurations were not reported as errors in Periodic mode when the enabled output pin did not match the selected counter clear source.
      • Renamed the FSP Configuration property items "MTIOCnA Pin Function" and "MTIOCnB Pin Function" to "TGRA I/O Pin Setting" and "TGRB I/O Pin Setting", respectively.
      • Fixed an issue where the compare match event used to trigger an A/D conversion request occurred one count later than the configured value.
        As a result of this fix, after updating FSP in an existing project, the compare match event for the A/D conversion request will occur one count earlier than in previous versions.
        To maintain the same timing as before, increase the configured compare match value by one count.
    • r_sci_b_i2c
      • Fixed an issue where an incorrect default value was configured for DMA Activation Request Source Select when using DMA integration.
    • r_sci_b_spi
      • Fixed an issue where an incorrect default value was configured for DMA Activation Request Source Select when using DMA integration.
    • r_sci_b_uart
      • Fixed an issue where an incorrect default value was configured for DMA Activation Request Source Select when using DMA integration.
    • r_scif_uart
      • Fixed an issue that allowed unsupported values to be configured for Baud Rate.
  • RZ/N series
    • Replaced handle_error() with assert() in example code. (r_bsc, r_bsc_nor, r_bsc_sdram, r_canfd, r_cmtw, r_dsmif, r_ether_phy, r_ether_selector, r_gmac, r_gmac_b, r_icu_error, r_icu_inter_cpu_irq, r_mtu3, r_pcie_ep, r_pcie_rc, r_shared_memory, r_xspi_hyper, rm_ethercat_ssc_port)
    • Added a note regarding data coherency when using the CPU cache to FSP Documentation.
    • Added a guide about memory barrier instruction to the FSP Documentation.
    • Fixed an issue where clicking the information icon for a module in the Stacks tab did not always open the corresponding FSP Documentation.
    • Added a guide about memory barrier instruction to the FSP Documentation. (r_bsc, r_bsc_nor, r_bsc_sdram, r_pcie_ep, r_pcie_rc, r_xspi_hyper, r_xspi_ospi, r_xspi_qspi)
    • Added a note regarding data coherency when using the CPU cache to FSP Documentation. (r_dmac, r_iic_master, r_iic_slave, r_sci_i2c, r_sci_spi, r_sci_uart, r_spi, r_xspi_ospi, r_xspi_qspi)
    • Added an explanation of interrupt configuration when using the example code to the FSP Documentation. (r_bsc, r_dmac, r_doc, r_pcie_rc, r_wdt)
    • Added example code to the FSP Documentation. (r_ether_phy, r_ethsw, r_gmac, r_gmac_b)
    • bsp
      • Added a memory region definition to allow the CR52 core to access its own TCM via AXIS.
      • Corrected the minimum value of LDR_ADDR_NML for eMMC boot from 0x1000 to 0x400.
      • Corrected the command for Change Program Location in the FSP Documentation.
      • Updated the DDR access processing in accordance with the update to the DDR parameter generation tool.
      • Added board-related information to the Board Description and Board Details sections.
      • Added the usage of OTFDE to the FSP Documentation.
      • Added notes regarding Register Protection to the FSP Documentation.
    • r_canfd
      • Updated the SJW value setting of the Nominal Data Rate to match the RZ/N2H Hardware Manual (Rev. 1.20) and RZ/N2L Hardware Manual (Rev. 1.40).
    • r_dmac
      • Optimized the R_DMAC_Reset() to reduce processing overhead.
    • r_elc
      • Added unsupported features to the FSP Documentation to match the RZ/N2L Hardware Manual (Rev. 1.40).
    • r_ether_phy
      • Added an Auto-MDIX option to the FSP Configuration.
      • Modified the FSP Configuration to display an error message when Autonegotiation is set to OFF while Speed is set to 1000 Mbps.
      • Added checks in the FSP Configuration for the number of available channels and the MDIO type for each MPU.
    • r_gmac
      • Fixed a bug where pause frames could not be sent or received when using GMAC with ETHSW.
    • r_gmac_b
      • Corrected the MAC_Configuration.FES bit setting according to the Hardware Manual.
      • Fixed a bug where pause frames could not be sent or received when using GMAC with ETHSW.
    • r_gpt
      • Updated validity checks for setting required for interrupts in FSP Configuration.
      • Updated the FSP Configuration to display a warning message if the settings required to use GPT_SEL (Interrupt) are missing.
      • Fixed an issue where the compare match event used to trigger an A/D conversion request occurred one count later than the configured value.
        As a result of this fix, after updating FSP in an existing project, the compare match event for the A/D conversion request will occur one count earlier than in previous versions.
        To maintain the same timing as before, increase the configured compare match value by one count.
    • r_ioport
      • Added a note regarding the arguments of R_IOPORT_PortDirectionSet() to the FSP Documentation.
    • r_mtu3
      • Added a mechanism to apply the r_mtu3 configuration settings to r_mtu3_three_phase.
      • Fixed an issue where invalid pin output configurations were not reported as errors in Periodic mode when the enabled output pin did not match the selected counter clear source.
      • Renamed the FSP Configuration property items "MTIOCnA Pin Function" and "MTIOCnB Pin Function" to "TGRA I/O Pin Setting" and "TGRB I/O Pin Setting", respectively.
      • Fixed an issue where the compare match event used to trigger an A/D conversion request occurred one count later than the configured value.
        As a result of this fix, after updating FSP in an existing project, the compare match event for the A/D conversion request will occur one count earlier than in previous versions.
        To maintain the same timing as before, increase the configured compare match value by one count.
    • r_pcie_ep
      • Updated validity checks for 64-bit settings and BAR overlap settings in FSP Configuration.
      • Expanded the description of memory access in the Features section of the FSP Documentation.
      • Added a description of BAR settings in the FSP Documentation.
      • Updated the window configuration example in the FSP Documentation.
      • Updated the description of the AXI access address translation formula in the FSP Documentation.
    • r_pcie_rc
      • Expanded the description of memory access in the Features section of the FSP Documentation.
      • Reviewed the example code for configuration settings from the RC to the EP.
      • Added a description of BAR settings in the FSP Documentation.
      • Updated the window configuration example in the FSP Documentation.
      • Updated validity checks for 64-bit settings and BAR overlap settings in FSP Configuration.
      • Updated the description of the AXI access address translation formula in the FSP Documentation.
    • r_rsip_protected
      • Fixed a bug where the ECDH and KDF buffer size could be insufficient when using brainpoolP384r1 or brainpoolP512r1.
      • Changed the default configuration to enable secp256k1, secp521r1, brainpoolP512r1, KDF HMAC-SHA384, and KDF HMAC-SHA512.
    • r_usb_basic
      • Changed R_USB_Read() and R_USB_Write() to validate the data size even when parameter checking is disabled.
      • Fixed a bug where execution could hang during initialization in the second call to the Open function after opening and closing once.
      • Removed unnecessary interrupt handlers.
      • Fixed an issue where R_USB_PeriControlDataGet(), R_USB_PeriControlDataSet(), R_USB_PeriControlStatusSet(), and R_USB_HostControlTransfer() returned success even when R_USB_Open() had not been called.
      • Renamed functions of usbf isr.
    • r_usb_hhid
      • Revised the description of the limitations in the FSP Documentation to make it easier to understand.
    • r_usb_pcdc
      • Fixed a bug where the CDC driver would not be installed unless 2 (ACM) was specified as the Subclass in the Device Descriptor in the case of ARM Windows, .
    • r_xspi_hyper
      • Fixed an issue where manual commands were sent only to the most recently opened CS space when a unit was connected to multiple CS spaces.
      • Changed the type of the first argument of R_XSPI_HYPER_AccessSpaceSet(), R_XSPI_HYPER_Write(), R_XSPI_HYPER_Erase(), R_XSPI_HYPER_StatusGet(), R_XSPI_HYPER_AutoCalibrate(), R_XSPI_HYPER_Close() to const.
      • Changed the number of dummy reads in the example code to match the specifications of the HyperRAM mounted on the RZ/N series evaluation boards.
    • r_xspi_ospi
      • Fixed an issue where manual commands were sent only to the most recently opened CS space when a unit was connected to multiple CS spaces.
      • Added a parameter check to verify that the write data does not cross a Flash memory page boundary.
    • r_xspi_qspi
      • Added a parameter check to verify that the write data does not cross a Flash memory page boundary.
      • Fixed an issue where manual commands were sent only to the most recently opened CS space when a unit was connected to multiple CS spaces.
      • Changed the initial value of the dummy cycle for the Read command.
  • RZ/T series
    • Replaced handle_error() with assert() in example code. (r_bsc, r_bsc_nor, r_bsc_sdram, r_canfd, r_dsmif, r_elc, r_ether_phy, r_ether_selector, r_gmac, r_gmac_b, r_icu_error, r_icu_inter_cpu_irq, r_mtu3, r_pcie_rc, r_pcie_ep, r_shared_memory, r_xspi_hyperbus, rm_ethercat_ssc_port)
    • Added a note regarding data coherency when using the CPU cache to FSP Documentation.
    • Added a guide about memory barrier instruction to the FSP Documentation.
    • Fixed an issue where clicking the information icon for a module in the Stacks tab did not always open the corresponding FSP Documentation.
    • Added a guide about memory barrier instruction to the FSP Documentation. (r_bsc, r_bsc_nor, r_bsc_sdram, r_pcie_ep, r_pcie_rc, r_xspi_hyper, r_xspi_ospi, r_xspi_qspi)
    • Added a note regarding data coherency when using the CPU cache to FSP Documentation. (r_dmac, r_iic_master, r_iic_slave, r_sci_i2c, r_sci_spi, r_sci_uart, r_spi, r_xspi_ospi, r_xspi_qspi)
    • Added an explanation of interrupt configuration when using the example code to the FSP Documentation. (r_bsc, r_dmac, r_doc, r_pcie_rc, r_wdt)
    • Added example code to the FSP Documentation. (r_ether_phy, r_ethsw, r_gmac, r_gmac_b)
    • bsp
      • Added a memory region definition to allow the CR52 core to access its own TCM via AXIS.
      • Corrected the minimum value of LDR_ADDR_NML for eMMC boot from 0x1000 to 0x400.
      • Corrected the command for Change Program Location in the FSP Documentation.
      • Updated the DDR access processing in accordance with the update to the DDR parameter generation tool.
      • Added board-related information to the Board Description and Board Details sections.
      • Added the usage of OTFDE to the FSP Documentation.
      • Added notes regarding Register Protection to the FSP Documentation.
    • r_canfd
      • Updated the SJW value setting of the Nominal Data Rate to match the RZ/T2M Hardware Manual (Rev. 1.30), RZ/T2ME Hardware Manual (Rev. 1.10) and RZ/T2L Hardware Manual (Rev. 1.30).
    • r_dmac
      • Optimized the R_DMAC_Reset() to reduce processing overhead.
    • r_elc
      • Added a note stating that input capture is not supported when MTU is selected for an ELC user event to match the RZ/T2M Hardware Manual (Rev. 1.30), RZ/T2ME Hardware Manual (Rev. 1.10) and RZ/T2L Hardware Manual (Rev. 1.30).
    • r_ether_phy
      • Added an Auto-MDIX option to the FSP Configuration.
      • Modified the FSP Configuration to display an error message when Autonegotiation is set to OFF while Speed is set to 1000 Mbps.
      • Added checks in the FSP Configuration for the number of available channels and the MDIO type for each MPU.
    • r_gmac
      • Fixed a bug where pause frames could not be sent or received when using GMAC with ETHSW.
    • r_gmac_b
      • Corrected the MAC_Configuration.FES bit setting according to the Hardware Manual.
      • Fixed a bug where pause frames could not be sent or received when using GMAC with ETHSW.
    • r_gpt
      • Updated validity checks for setting required for interrupts in FSP Configuration.
      • Updated the FSP Configuration to display a warning message if the settings required to use GPT_SEL (Interrupt) are missing.
      • Fixed an issue where the compare match event used to trigger an A/D conversion request occurred one count later than the configured value.
        As a result of this fix, after updating FSP in an existing project, the compare match event for the A/D conversion request will occur one count earlier than in previous versions.
        To maintain the same timing as before, increase the configured compare match value by one count.
    • r_ioport
      • Added a note regarding the arguments of R_IOPORT_PortDirectionSet() to the FSP Documentation.
    • r_mtu3
      • Added a mechanism to apply the r_mtu3 configuration settings to r_mtu3_three_phase.
      • Fixed an issue where invalid pin output configurations were not reported as errors in Periodic mode when the enabled output pin did not match the selected counter clear source.
      • Renamed the FSP Configuration property items "MTIOCnA Pin Function" and "MTIOCnB Pin Function" to "TGRA I/O Pin Setting" and "TGRB I/O Pin Setting", respectively.
      • Fixed an issue where the compare match event used to trigger an A/D conversion request occurred one count later than the configured value.
        As a result of this fix, after updating FSP in an existing project, the compare match event for the A/D conversion request will occur one count earlier than in previous versions.
        To maintain the same timing as before, increase the configured compare match value by one count.
    • r_pcie_ep
      • Updated validity checks for 64-bit settings and BAR overlap settings in FSP Configuration.
      • Expanded the description of memory access in the Features section of the FSP Documentation.
      • Added a description of BAR settings in the FSP Documentation.
      • Updated the window configuration example in the FSP Documentation.
      • Updated the description of the AXI access address translation formula in the FSP Documentation.
    • r_pcie_rc
      • Expanded the description of memory access in the Features section of the FSP Documentation.
      • Reviewed the example code for configuration settings from the RC to the EP.
      • Added a description of BAR settings in the FSP Documentation.
      • Updated the window configuration example in the FSP Documentation.
      • Updated validity checks for 64-bit settings and BAR overlap settings in FSP Configuration.
      • Updated the description of the AXI access address translation formula in the FSP Documentation.
    • r_rsip_protected
      • Fixed a bug where the ECDH and KDF buffer size could be insufficient when using brainpoolP384r1 or brainpoolP512r1.
      • Changed the default configuration to enable secp256k1, secp521r1, brainpoolP512r1, KDF HMAC-SHA384, and KDF HMAC-SHA512.
    • r_tsu_b
      • Changed the event name notation from TSU0_ADI/TSU0_ADCMPI to TSU0_TSUADI/TSU0_TSUADCMPI.
    • r_usb_basic
      • Changed R_USB_Read() and R_USB_Write() to validate the data size even when parameter checking is disabled.
      • Fixed a bug where execution could hang during initialization in the second call to the Open function after opening and closing once.
      • Removed unnecessary interrupt handlers.
      • Fixed an issue where R_USB_PeriControlDataGet(), R_USB_PeriControlDataSet(), R_USB_PeriControlStatusSet(), and R_USB_HostControlTransfer() returned success even when R_USB_Open() had not been called.
      • Renamed functions of usbf isr.
    • r_usb_hhid
      • Revised the description of the limitations in the FSP Documentation to make it easier to understand.
    • r_usb_pcdc
      • Fixed a bug where the CDC driver would not be installed unless 2 (ACM) was specified as the Subclass in the Device Descriptor in the case of ARM Windows, .
    • r_xspi_hyper
      • Fixed an issue where manual commands were sent only to the most recently opened CS space when a unit was connected to multiple CS spaces.
      • Changed the type of the first argument of R_XSPI_HYPER_AccessSpaceSet(), R_XSPI_HYPER_Write(), R_XSPI_HYPER_Erase(), R_XSPI_HYPER_StatusGet(), R_XSPI_HYPER_AutoCalibrate(), R_XSPI_HYPER_Close() to const.
      • Changed the number of dummy reads in the example code to match the specifications of the HyperRAM mounted on the RZ/T series evaluation boards.
    • r_xspi_ospi
      • Fixed an issue where manual commands were sent only to the most recently opened CS space when a unit was connected to multiple CS spaces.
      • Added a parameter check to verify that the write data does not cross a Flash memory page boundary.
    • r_xspi_qspi
      • Added a parameter check to verify that the write data does not cross a Flash memory page boundary.
      • Fixed an issue where manual commands were sent only to the most recently opened CS space when a unit was connected to multiple CS spaces.
  • RZ/V series
    • Fixed an issue where clicking the information icon for a module in the Stacks tab did not always open the corresponding FSP Documentation.
    • bsp
      • Added board-related information to the Board Description and Board Details sections.
    • r_canfd
      • Fixed an issue where valid values configured for Sample Point (%) were sometimes incorrectly reported as errors.
    • r_gmac
      • Fixed an issue where the GMAC driver did not operate correctly when booting from Cortex-M33 core on RZ/V2H devices.
    • r_i3c_b
      • Fixed incorrect addresses and register accesses for the DATBASm (m=1-7) and EXDATBAS registers.
      • Fixed the maximum device count and FIFO buffer depth.
      • Fixed an issue where transmitted data could contain data from a previous transmission.
    • r_gtm
      • Fixed an issue where the count period was one count longer than the configured value.
    • r_gpt
      • Fixed an issue where the compare match event used to trigger an A/D conversion request occurred one count later than the configured value.
        As a result of this fix, after updating FSP in an existing project, the compare match event for the A/D conversion request will occur one count earlier than in previous versions.
        To maintain the same timing as before, increase the configured compare match value by one count.
    • r_ioport
      • Fixed an issue where a build error occurred when changing the Name property value from the Property menu.
      • Added a note regarding the arguments of R_IOPORT_PortDirectionSet() to the FSP Documentation.
    • r_mtu3
      • Fixed an issue where invalid pin output configurations were not reported as errors in Periodic mode when the enabled output pin did not match the selected counter clear source.
      • Renamed the FSP Configuration property items "MTIOCnA Pin Function" and "MTIOCnB Pin Function" to "TGRA I/O Pin Setting" and "TGRB I/O Pin Setting", respectively.
      • Fixed an issue where the compare match event used to trigger an A/D conversion request occurred one count later than the configured value.
        As a result of this fix, after updating FSP in an existing project, the compare match event for the A/D conversion request will occur one count earlier than in previous versions.
        To maintain the same timing as before, increase the configured compare match value by one count.
      • Fixed an issue where no error was reported when A/D Converter Activation by TGRA Input Capture/Compare Match, which is not supported for Channel 8, was enabled.
    • r_sci_b_i2c
      • Fixed an issue where an incorrect default value was configured for DMA Activation Request Source Select when using DMA integration.
    • r_sci_b_spi
      • Fixed an issue where an incorrect default value was configured for DMA Activation Request Source Select when using DMA integration.
    • r_sci_b_uart
      • Fixed an issue where an incorrect default value was configured for DMA Activation Request Source Select when using DMA integration.
    • r_scif_uart
      • Fixed an issue that allowed unsupported values to be configured for Baud Rate.

Known Issues

  • All device series
    • This FSP version requires e2 studio 2026-07 or later.
      Using this FSP version with an earlier version of e2 studio may cause project generation or build failures.
      To avoid this issue, use the platform installer bundled with e2 studio 2026-07, or ensure that e2 studio 2026-07 (or later) is installed when installing software packs separately.
      For separate installation instructions, refer to the Getting Started with Flexible Software Package.
  • RZ/A series
    • None
  • RZ/G series
    • None
  • RZ/N series
    • FreeRTOS+FAT format process is not executed correctly.
    • In the secondary project for multiprocessing, no error occurs when there is a conflict in a resource used with the preceding project.
    • No Error Occurs when entering out-of-range values for window parameters in r_pcie_ep and r_pcie_rc module configurations.
    • Address space of DDR and PCIE cannot be used in the secondary (or later) projects with flash boot mode.
    • r_gmac_b module cannot use zero-copy mode.
    • Pin names according to unit and channel numbers are not displayed in r_gpt module configurations.
    • *length_bytes is an input/output parameter of R_GMAC_Read()/R_GMAC_B_Read() and must be reset before every call.
    • Limit the requested transfer size to 2048 bytes or less when using DMA transfer mode of a USB peripheral.
    • r_ether_phy module does not operate correctly when multiple KSZ series PHYs are enabled simultaneously.
  • RZ/T series
    • In multiprocessing, a configuration error occurs when “r_gpt” module is used for both projects for CPU0 and CPU1.
    • FreeRTOS+FAT format process is not executed correctly.
    • In the secondary project for multiprocessing, no error occurs when there is a conflict in a resource used with the preceding project.
    • No Error Occurs when entering out-of-range values for window parameters in r_pcie_ep and r_pcie_rc module configurations.
    • Address space of DDR and PCIE cannot be used in the secondary (or later) projects with flash boot mode.
    • r_gmac_b module cannot use zero-copy mode.
    • Pin names according to unit and channel numbers are not displayed in r_gpt module configurations.
    • *length_bytes is an input/output parameter of R_GMAC_Read()/R_GMAC_B_Read() and must be reset before every call.
    • Limit the requested transfer size to 2048 bytes or less when using DMA transfer mode of a USB peripheral.
    • Building generated code fails when Context parameter of r_layer3_switch module is set to a non-NULL value.
    • r_ether_phy module does not operate correctly when multiple KSZ series PHYs are enabled simultaneously.
  • RZ/V series
    • None

Supported Components

For RZ/A series

Category Components RZ/A3UL RZ/A3M
OS FreeRTOS ✓ ✓
AzureRTOS ThreadX ✓ ✓
Middleware FreeRTOS+TCP ✓ -
FreeRTOS+FAT ✓ ✓
FreeRTOS+POSIX - ✓
FileX ✓ ✓
USBX ✓ ✓
GUIX ✓ ✓
NetX Duo ✓ -
RealityAI connections (rm_rai_data_shipper, rm_rai_data_collector) ✓ -
OpenH264 - ✓
LVGL ✓ ✓
HAL Driver ADC (r_adc_c) ✓ -
CANFD (r_canfd) ✓ -
CRU (r_cru) ✓ -
DMAC (r_dmac) ✓ ✓
D/AVE 2D Port Interface (r_drw) - ✓
Ether (r_gether, r_gether_phy) ✓ -
GTM (r_gtm) ✓ ✓
I2C Master (r_riic_master) ✓ ✓
I2C Slave (r_riic_slave) ✓ ✓
INTC_IRQ (r_intc_irq) ✓ ✓
INTC_NMI (r_intc_nmi) ✓ ✓
INTC_TINT (r_intc_tint) ✓ ✓
I/O Ports (r_ioport) ✓ ✓
ISU (r_isu) ✓ -
LCDC (r_lcdc) ✓ ✓
MIPI DSI (r_mipi_dsi_b, r_mipi_dsi_phy_b) - ✓
MTU3 (r_mtu3) ✓ ✓
RSPI (r_rspi) ✓ ✓
SCI_uart (r_sci_uart) ✓ ✓
SCIF_uart (r_scif_uart) ✓ ✓
SDHI (r_sdhi) ✓ ✓
SPIBSC (r_spibsc) ✓ ✓
SSI (r_ssi) ✓ ✓
USB HHID (r_usb_hhid) ✓ ✓
USB HMSC (r_usb_msc) ✓ ✓
USB PCDC (r_usb_pcdc) ✓ ✓
WDT (r_wdt) ✓ ✓

For RZ/G series

Category Components RZ/G2L RZ/G2LC RZ/G2UL RZ/G3S RZ/G3E RZ/G3L RZ/G3SE
OS FreeRTOS ✓ ✓ ✓ ✓ ✓ ✓ ✓
Middleware OpenAMP ✓ ✓ ✓ ✓ ✓ ✓ ✓
EthosU NA NA NA NA ✓ NA NA
FlatBuffers NA NA NA NA ✓ NA NA
GEMM Low Precision NA NA NA NA ✓ NA NA
RUY NA NA NA NA ✓ NA NA
TFLite Micro NA NA NA NA ✓ NA NA
HAL Driver ADC (r_adc_c) ✓ NA ✓ ✓ NA ✓ ✓
ADC_E (r_adc_e) NA NA NA NA ✓ NA NA
CANFD (r_canfd) ✓ ✓ ✓ ✓ ✓ ✓ ✓
CMTW (r_cmtw) NA NA NA NA ✓ NA NA
CRC (r_crc) NA NA NA NA ✓ NA NA
DMAC (r_dmac_b) NA NA NA ✓ ✓ ✓ ✓
ELC (r_elc) NA NA NA NA ✓ NA NA
GPT (r_gpt) ✓ ✓ N/A ✓ ✓ ✓ ✓
GTM (r_gtm) ✓ ✓ ✓ ✓ ✓ ✓ ✓
I2C Master (r_riic_master) ✓ ✓ ✓ ✓ ✓ ✓ ✓
I2C Slave (r_riic_slave) NA NA NA NA ✓ ✓ ✓
I3C_B (r_i3c_b) NA NA NA NA ✓ ✓ ✓
INTC_IRQ (r_intc_irq) ✓ ✓ ✓ ✓ ✓ ✓ ✓
INTC_NMI (r_intc_nmi) NA NA NA ✓ ✓ ✓ ✓
INTC_TINT (r_intc_tint) NA NA NA NA ✓ ✓ ✓
I/O Ports (r_ioport) ✓ ✓ ✓ ✓ ✓ ✓ ✓
LCDC (r_lcdc) NA NA NA NA NA ✓ ✓
MIPI DSI (r_mipi_dsi_b, r_mipi_phy_b) NA NA NA NA NA ✓ ✓
MHU (r_mhu_ns, r_mhu_s,
r_mhu_ns_swint_get, r_mhu_ns_swint_set)		 ✓ ✓ ✓ ✓ NA ✓ ✓
MHU_B (r_mhu_b_ns, r_mhu_b_s, r_mhu_b_ns_swint_get, r_mhu_b_ns_swint_set) NA NA NA NA ✓ NA NA
MTU3 (r_mtu3) ✓ ✓ ✓ ✓ NA ✓ ✓
PDM (r_pdm) NA NA NA NA ✓ ✓ ✓
POEG (r_poeg) ✓ ✓ NA ✓ ✓ ✓ ✓
RSPI (r_rspi) ✓ ✓ ✓ ✓ NA NA NA
RTC (r_rtc) NA NA NA NA ✓ ✓ ✓
SCI (r_sci_uart) ✓ ✓ ✓ ✓ NA NA NA
SCI_B (r_sci_b_i2c, r_sci_b_spi, r_sci_b_uart) NA NA NA NA ✓ ✓ ✓
SCIF (r_scif_uart) ✓ ✓ ✓ ✓ ✓ ✓ ✓
SPI_B (r_spi_b) NA NA NA NA ✓ ✓ ✓
TSU_B (r_tsu_b) NA NA NA NA ✓ NA NA
WDT (r_wdt) ✓ ✓ ✓ ✓ ✓ ✓ ✓
xSPI_qspi (r_xspi_qspi) NA NA NA ✓ ✓ ✓ ✓

For RZ/N series

Category Module category Components RZ/N2L RZ/N2H
OS - FreeRTOS ✓ ✓
Middleware - OpenAMP NA ✓
Networking EtherCAT SSC Port (rm_ethercat_ssc_port) ✓ ✓
FreeRTOS+TCP Wrapper to ethernet driver (rm_freertos_plus_tcp) ✓ ✓
RTOS FreeRTOS Port (rm_freertos_port) ✓ ✓
Storage Block Media SD/MMC (rm_block_media_sdmmc) NA ✓
Block Media USB (rm_block_media_usb) ✓ ✓
Block Media Custom Implementation (rm_block_media_user) ✓ ✓
FreeRTOS+FAT Port for RZN (rm_freertos_plus_fat) ✓ ✓
HAL Driver Analog ADC (r_adc) ✓ ✓
Delta-Sigma Modulator Interface (r_dsmif) ✓ ✓
Connectivity CAN FD (r_canfd) ✓ ✓
I2C Master (r_iic_master) ✓ ✓
I2C Slave (r_iic_slave) ✓ ✓
PCIE_EP (r_pcie_ep) NA ✓
PCIE_RC (r_pcie_rc) NA ✓
I2C Master (r_sci_i2c) ✓ ✓
SMCI (r_sci_smci) ✓ ✓
SPI (r_sci_spi) ✓ ✓
UART (r_sci_uart) ✓ ✓
SPI (r_spi) ✓ ✓
USB (r_usb_basic) ✓ ✓
USB HCDC (r_usb_hcdc) ✓ ✓
USB HHID (r_usb_hhid) ✓ ✓
USB HMSC (r_usb_hmsc) ✓ ✓
USB Host Vendor class (r_usb_hvnd) ✓ ✓
USB PCDC (r_usb_pcdc) ✓ ✓
USB PHID (r_usb_phid) ✓ ✓
USB PMSC (r_usb_pmsc) ✓ ✓
USB PVND (r_usb_pvnd) ✓ ✓
Graphics LCD (r_lcdc) NA ✓
Input External IRQ (r_icu) ✓ ✓
Monitoring CRC (r_crc) ✓ ✓
Data Operation Circuit (r_doc) ✓ ✓
Watchdog (r_wdt) ✓ ✓
Networking Ethernet (r_ether_phy) ✓ ✓
Ethernet SELECTOR (r_ether_selector) ✓ ✓
Ethernet Switch (r_ethsw) ✓ ✓
Ethernet (r_gmac) ✓ NA
Ethernet (r_gmac_b) NA ✓
Security Renesas Secure IP (r_rsip_protected) ✓ ✓
Sensor Temperature Sensor Unit (r_tsu) ✓ NA
Temperature Sensor Unit (r_tsu_b) NA ✓
Storage BSC NOR (r_bsc_nor) ✓ ✓
SD/MMC (r_sdhi) NA ✓
xSPI HyperBus (r_xspi_hyper) ✓ ✓
OSPI Flash (r_xspi_ospi) ✓ ✓
QSPI (r_xspi_qspi) ✓ ✓
System BSC (r_bsc) ✓ ✓
SDRAM (r_bsc_sdram) ✓ NA
Clock Generation Circuit (r_cgc) ✓ ✓
Event Link Controller (r_elc) ✓ ✓
ICU ERROR (r_icu_error) ✓ ✓
Inter-CPU IRQ (r_icu_inter_cpu_irq) NA ✓
I/O Port (r_ioport) ✓ ✓
Shared Memory (r_shared_memory) NA ✓
Timers Timer, Compare Match (r_cmt) ✓ ✓
Timer, Compare Match W (r_cmtw) ✓ ✓
Timer, General PWM (r_gpt) ✓ ✓
Three-Phase PWM (r_gpt_three_phase) ✓ ✓
Timer, Multi-Function (r_mtu3) ✓ ✓
Three-Phase PWM (r_mtu3_three_phase) ✓ ✓
Port Output Enable for MTU3 (r_poe3) ✓ ✓
Port Output Enable for GPT (r_poeg) ✓ ✓
Realtime Clock (r_rtc) ✓ ✓
Transfer Transfer (r_dmac) ✓ ✓

For RZ/T series

Category Module category Components RZ/T2M RZ/T2L RZ/T2ME RZ/T2H
OS - FreeRTOS ✓ ✓ ✓ ✓
Middleware - OpenAMP NA NA NA ✓
Networking EtherCAT SSC Port (rm_ethercat_ssc_port) ✓ ✓ ✓ ✓
FreeRTOS+TCP Wrapper to ethernet driver (rm_freertos_plus_tcp) ✓ ✓ ✓ ✓
RTOS FreeRTOS Port (rm_freertos_port) ✓ ✓ ✓ ✓
Storage Block Media SD/MMC (rm_block_media_sdmmc) NA NA NA ✓
Block Media USB (rm_block_media_usb) ✓ ✓ ✓ ✓
Block Media Custom Implementation (rm_block_media_user) ✓ ✓ ✓ ✓
FreeRTOS+FAT Port for RZT (rm_freertos_plus_fat) ✓ ✓ ✓ ✓
HAL Driver Analog ADC (r_adc) ✓ ✓ ✓ ✓
Delta-Sigma Modulator Interface (r_dsmif) ✓ ✓ ✓ ✓
Connectivity CAN FD (r_canfd) ✓ ✓ ✓ ✓
I2C Master (r_iic_master) ✓ ✓ ✓ ✓
I2C Slave (r_iic_slave) ✓ ✓ ✓ ✓
PCIE_EP (r_pcie_ep) NA NA NA ✓
PCIE_RC (r_pcie_rc) NA NA NA ✓
I2C Master (r_sci_i2c) ✓ ✓ ✓ ✓
SMCI (r_sci_smci) ✓ ✓ ✓ ✓
SPI (r_sci_spi) ✓ ✓ ✓ ✓
UART (r_sci_uart) ✓ ✓ ✓ ✓
SPI (r_spi) ✓ ✓ ✓ ✓
USB (r_usb_basic) ✓ ✓ ✓ ✓
USB HCDC (r_usb_hcdc) ✓ ✓ ✓ ✓
USB HHID (r_usb_hhid) ✓ ✓ ✓ ✓
USB HMSC (r_usb_hmsc) ✓ ✓ ✓ ✓
USB Host Vendor class (r_usb_hvnd) ✓ ✓ ✓ ✓
USB PCDC (r_usb_pcdc) ✓ ✓ ✓ ✓
USB PHID (r_usb_phid) ✓ ✓ ✓ ✓
USB PMSC (r_usb_pmsc) ✓ ✓ ✓ ✓
USB PVND (r_usb_pvnd) ✓ ✓ ✓ ✓
Graphics LCD (r_lcdc) NA NA NA ✓
Input External IRQ (r_icu) ✓ ✓ ✓ ✓
Monitoring CRC (r_crc) ✓ ✓ ✓ ✓
Data Operation Circuit (r_doc) ✓ ✓ ✓ ✓
Watchdog (r_wdt) ✓ ✓ ✓ ✓
Networking Ethernet (r_ether_phy) ✓ ✓ ✓ ✓
Ethernet SELECTOR (r_ether_selector) ✓ ✓ ✓ ✓
Ethernet Switch (r_ethsw) ✓ ✓ ✓ ✓
Ethernet (r_gmac) ✓ ✓ ✓ NA
Ethernet (r_gmac_b) NA NA NA ✓
HSR/PRP Switch (r_hpsw) NA NA NA NA
Ethernet Generic PTP Timer (r_gptp) NA NA NA NA
Layer3 Ethernet Switch (r_layer3_switch) NA NA NA NA
Ethernet (r_rmac) NA NA NA NA
Security Renesas Secure IP (r_rsip_protected) ✓ ✓ ✓ ✓
Sensor Temperature Sensor Unit (r_tsu) ✓ ✓ ✓ NA
Temperature Sensor Unit (r_tsu_b) NA NA NA ✓
Storage BSC NOR (r_bsc_nor) ✓ ✓ ✓ ✓
SD/MMC (r_sdhi) NA NA NA ✓
NAND Flash (r_nandc) NA NA NA NA
xSPI HyperBus (r_xspi_hyper) ✓ ✓ ✓ ✓
OSPI Flash (r_xspi_ospi) ✓ ✓ ✓ ✓
QSPI (r_xspi_qspi) ✓ ✓ ✓ ✓
System BSC (r_bsc) ✓ ✓ ✓ ✓
SDRAM (r_bsc_sdram) ✓ ✓ ✓ NA
Clock Generation Circuit (r_cgc) ✓ ✓ ✓ ✓
Event Link Controller (r_elc) ✓ ✓ ✓ ✓
ICU ERROR (r_icu_error) ✓ ✓ ✓ ✓
Inter-CPU IRQ (r_icu_inter_cpu_irq) ✓ NA ✓ ✓
I/O Port (r_ioport) ✓ ✓ ✓ ✓
Shared Memory (r_shared_memory) ✓ NA ✓ ✓
Timers Timer, Compare Match (r_cmt) ✓ ✓ ✓ ✓
Timer, Compare Match W (r_cmtw) ✓ ✓ ✓ ✓
Timer, General PWM (r_gpt) ✓ ✓ ✓ ✓
Three-Phase PWM (r_gpt_three_phase) ✓ ✓ ✓ ✓
Timer, Multi-Function (r_mtu3) ✓ ✓ ✓ ✓
Three-Phase PWM (r_mtu3_three_phase) ✓ ✓ ✓ ✓
Port Output Enable for MTU3 (r_poe3) ✓ ✓ ✓ ✓
Port Output Enable for GPT (r_poeg) ✓ ✓ ✓ ✓
Realtime Clock (r_rtc) ✓ ✓ ✓ ✓
Transfer Transfer (r_dmac) ✓ ✓ ✓ ✓

For RZ/V series

Category Components RZ/V2L(Cortex-M33) RZ/V2H(Cortex-M33) RZ/V2H(Cortex-R8) RZ/V2N(Cortex-M33)
OS FreeRTOS ✓ ✓ ✓ ✓
Middleware OpenAMP ✓ ✓ ✓ ✓
FreeRTOS+TCP NA NA ✓ NA
HAL Driver ADC_C(r_adc_c) ✓ NA NA NA
ADC_E(r_adc_e) NA ✓ ✓ ✓
CANFD(r_canfd) ✓ ✓ ✓ ✓
CMTW(r_cmtw) NA ✓ ✓ ✓
CRC(r_crc) NA ✓ ✓ ✓
DMAC_B(r_dmac_b) ✓ ✓ ✓ ✓
Ethernet(r_gmac_b, r_ether_phy) NA NA ✓ NA
ELC(r_elc) NA ✓ ✓ ✓
GPT(r_gpt) ✓ ✓ ✓ ✓
GTM(r_gtm) ✓ ✓ ✓ ✓
I3C_B(r_i3c_b) NA ✓ NA ✓
INTC_IRQ(r_intc_irq) ✓ ✓ ✓ ✓
INTC_NMI(r_intc_nmi) NA ✓ ✓ ✓
INTC_TINT(r_intc_tint) NA ✓ ✓ ✓
I/O Ports (r_ioport) ✓ ✓ ✓ ✓
MHU(r_mhu_ns, r_mhu_s, r_mhu_ns_swint_get, r_mhu_ns_swint_set) ✓ NA NA NA
MHU_B(r_mhu_b_ns, r_mhu_b_s, r_mhu_b_ns_swint_get, r_mhu_b_ns_swint_set) NA ✓ ✓ ✓
MTU3(r_mtu3) ✓ NA NA NA
PDM(r_pdm) NA ✓ NA ✓
POEG(r_poeg) ✓ ✓ ✓ ✓
I2C Master(r_riic_master) ✓ ✓ ✓ ✓
I2C Slave(r_riic_slave) NA ✓ ✓ ✓
RSPI(r_rspi) ✓ NA NA NA
RTC(r_rtc) NA ✓ ✓ ✓
SCIF(r_scif_uart) ✓ ✓ ✓ ✓
SCI_B(r_sci_b_i2c, r_sci_b_spi, r_sci_b_uart) NA ✓ ✓ ✓
SPI_B(r_spi_b) NA ✓ ✓ ✓
TSU_B(r_tsu_b) NA ✓ NA ✓
WDT(r_wdt) NA ✓ ✓ ✓
xSPI_qspi(r_xspi_qspi) NA ✓ NA ✓

Knowledge Base

Visit our knowledge base for other technical updates.

MD5 Checksums

  • RZ_FSP_Packs_v4.2.0.zip 8a1f1c4cf93e15947ae83b2a09827e24
  • RZ_FSP_Packs_v4.2.0.exe 100901442f7f93d8c2ca669376478086
  • fsp_documentation_v4.2.0.zip a66727fd3c2d6f09a3f0cd35dd8be378
  • setup_rzfsp_v4_2_0_e2s_v2026-07.exe 32a1bc005062f9205b62a6777f48d3aa
  • setup_rzfsp_v4_2_0_e2s_v2026-07.xz.run dd7c0a2e8b7f8eefa25ef660fe3321eb
  • setup_rzfsp_v4_2_0_rzsc_v2026-07.exe a0c86d7a2decdaac89b6f90cdf5e8e0f
  • setup_rzfsp_v4_2_0_rzsc_v2026-07.xz.run 8219d3d4ab02fad38fdb8d1cbbb595f3
  • SBOM_RZ_FSP_Packs_v4.2.0.spdx e3f1be02a4b11d9ac476721502a69feb
Assets 10
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