HDLBoard 1.0.0 — First release

The first working release of HDLBoard: write VHDL and watch it run on a virtual DE1-SoC board.

Edit VHDL, press Start, and flip switches and buttons while the LEDs and 7-segment displays react. Your design runs on real GHDL, not an approximation. It is built as a gentle first step into FPGA design for students, before timing analysis and beyond.

Highlights

• Real simulation. GHDL analyzes, elaborates and runs your VHDL. Its own output and errors,
  with file and line, appear in the console.
• Live DE1-SoC board. Clickable SW[9:0] and KEY_N[3:0], with LEDR[9:0] and
  HEX0_N…HEX5_N driven by the simulation.
• A small IDE. File explorer with upload and drag-and-drop, a tabbed editor with VHDL syntax
  highlighting, and resizable panes.
• Testbenches too. report and assert output prints live from a plain, portless testbench.
• Real-time pacing. Simulated time tracks real time, so a design's timing here predicts its
  timing on the board.
• Starter files. DE1_SoC.vhdl with the real DE1-SoC pin names, plus blinkTest.vhdl and keyCouter2Led.vhdl.

Install (Windows)

1. Download HDLBoard-Setup-1.0.0.exe below and run it.
2. The installer is not code-signed, so Windows SmartScreen will warn that the publisher is unknown. Choose More info → Run anyway.
3. Launch HDLBoard from the Start menu or the desktop shortcut.

No Node.js, GHDL or WSL is needed: GHDL 5.0.1 is bundled. It installs for the current user only and never asks for administrator rights.

Pre-built VirtualBox Appliance — HDLBoard.ova

Ready-to-run VirtualBox image for HDLBoard — a VHDL IDE with interactive board simulation.

Requirements: VirtualBox installed from virtualbox.org

Install:

1. Download HDLBoard.ova
2. Open VirtualBox → File → Import Appliance
3. Select the downloaded file → Import
4. Click Start to boot the VM
5. In a web browser, go to http://127.0.0.1

*** Login:** username: root / password: student2026 (please change it)

Manual build

To run HDLBoard in a browser, or to build it yourself, see BUILDING.md.

Known limitations

• Files and edits live in memory only. Reloading resets the project to the starter files.
• A design that divides the real 50 MHz clock down to a human-visible rate needs millions of simulated cycles per visible change and is impractical here. Use the optional CLOCK_500Hz port for a ready-divided clock. It is a simulator convenience, not a real board pin.

Built for PB1180 Programmerbare logiske kretser at USN. Licensed under GPL-2.0.