cortex-m v0.7.8

Soundness fix (breaking change)

The singleton! macro now requires the user to supply a critical-section implementation. The
previous behavior was to disable interrupts in the current core, which is unsound on multicore chips. By using critical-section the user can set
the implementation that's sound for their chip.

Not supplying an implementation will result in a linker error like rust-lld: error: undefined symbol: _critical_section_1_0_acquire.

To supply one, do either one of:

• For single-core chips running in privileged mode, enable feature critical-section-single-core in the cortex-m crate. This implementation disables interrupts in the current core and is equivalent to the behavior in previous versions.
• For other chips, enable a suitable implementation that ensures locking across cores. They are typically supplied by HAL crates with a feature named critical-section-impl or similar.

Library crates generally should not enable a critical section implementation, only the end user (who is building the final binary) should.

Deprecated

• The inline-asm feature is now a currently a no-op, will be removed in a future major version

Changed

• Updated to edition 2024.
• MSRV is 1.85 to match cortex-m-rt crate
• Add enter_unprivileged function to switch to unprivileged mode (on the Process Stack, or PSP)
• Updated references from 'Cortex-M Team' to 'Arm Team'
• Add ITNS field to NVIC peripheral.
• Expose more bits from within SCR.
• Refactor asm code to remove need for very old nightly toolchain. Everything is now compiled with
  the default toolchain.
• The code should be clippy clean on all supported configurations now.
• Add embedded-hal 1.0 delays.
• Changed number of cycles performed in asm::delay() to guarantee that the
  number of CPU cycles consumed is always at least the number of cycles
  requested, even on Cortex-M7 platforms with dual issue. For other CPUs
  the number of cycles is likely to be twice as long as before.

Fixed

• SCB::vect_active() now reads ICSR with a volatile access, preventing the load from being narrowed
  to a byte read that faults on word-only ICSR models.