Stabilize ppc inline assembly

[pmur]

This stabilizes inline assembly for PowerPC and PowerPC64.

Corresponding reference PR: rust-lang/reference#2056

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From the requirements of stabilization mentioned in #93335

Each architecture needs to be reviewed before stabilization:

• It must have clobber_abi.

Done in #146949.

• It must be possible to clobber every register that is normally clobbered by a function call.

Done in #131341

Similarly, preserves_flags is also implemented by this PR. Notably, the consensus was to make this option do nothing on powerpc.

• Generally review that the exposed register classes make sense.

The followings can be used as input/output:

• reg (r0, r[3-12], r[14-r28]): Any usable general-purpose register
• reg_nonzero (r[3-12], r[14-r28]): General-purpose registers, but excludes r0. This is needed for instructions which define r0 to be the value 0, such as register + immediate memory operations.
• freg (f[0-31]): 64 bit floating pointer registers

The following are clobber-only:

• ctr, lr, xer: commonly clobbered special-purpose registers used in inline asm
• cr (cr[0-7], cr): the condition register fields, or the entire condition register.
• vreg (v[0-31]): altivec/vmx register
• vsreg (vs[0-63]): vector-scalar register

The vreg and vsreg registers technically accept #[repr(simd)] types, but require the experimental altivec or vsx target features to be enabled. That work seems to be tracked here, #42743.

The following cannot be used as operands for inline asm:

• r2: the TOC pointer, required for most PIC code.
• r13: the TLS pointer
• r[29-30]: Reserved for internal usage by LLVM
• r31: the frame pointer
• vrsave: this is effectively an unused special-purpose register.

The following registers are unavailable:

• spe_acc, spefscr: These are available exclusively on the SPE target (the e500, not cell). I am not sure how these are actually used. I think they can be added later if needed.
• mma[0-7]: These are new "registers" available on Power10, they are 512b registers which overlay 4x vsx registers. They could be added if needed, however their usage is very specialized.
• ap, mq: I don't think these registers exist on any usable power target supported by gcc/llvm.
• fpscr: it is not modelled by gcc or llvm.
• vscr: clang/gcc accept this as a clobber, but do not actually save/restore it.

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cc @taiki-e
r? @Amanieu
@rustbot label +A-inline-assembly