Release 0.1.0

Changelog

What's Changed

• introduce existing codebase by @rykovv in #2

0.1.0 — Initial Release

A header-only C++20 library for safe, optimized hardware register operations.

Highlights

• 12 IEEE 1685 access types — RW, RO, WO, RC, RS, RW_0C, RW_1C, RW_0S, RW_1S, RW_1T, RW_O, RSVD with correct identity and mask semantics
• Compile-time safety — field widths, bit positions, and access permissions are enforced at compile time. Writing a read-only field or reading a write-only register produces a static_assert failure.
• RMW optimization — bus reads are skipped when all Read-Modify-Write-able bits are covered by the write, preventing unintended side effects on RC/RS fields
• Identity preservation — partial writes fill non-targeted special fields with their hardware no-op value, preventing accidental clears, sets, or toggles
• Bus abstraction — pluggable bus interface decouples register definitions from transport (memory-mapped, SPI, I2C, etc.)
• Single entry point — eval() accepts any mix of compile-time writes, runtime writes, lambda-based read-modify-write, and reads in a single call

Supported compilers

Standard	GCC	Clang
C++20	12 thru 16	14 thru 21

New Contributors

• @rykovv made their first contribution in #2

Full Changelog: https://github.com/rykovv/ros/commits/release-0.1.0