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Releases: searchsolved/Arcade_HyperDuel_MiSTer

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v1.1: Magical Error wo Sagase added (2026-07-19)

v1.1: Magical Error wo Sagase added (2026-07-19) Latest
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@searchsolved searchsolved released this 19 Jul 21:38
v1.1
3566ba2

Adds Magical Error wo Sagase (Technosoft/Jaleco, 1994), the second and only other game on the dual-68000 + Imagetek I4220 architecture. Same verified VDP, CRTC display window and renderer as Hyper Duel v1.0.

What's new

  • Magical Error wo Sagase: separate RBF (Magerror_20260719.rbf) and MRA
  • IKAOPLL (cycle-accurate YM2413 by Sehyeon Kim) replaces the YM2151 for this title
  • Shared RAM moved to SDRAM to fit the larger 128KB region the game uses
  • System glue parameterised: one RTL tree, GAME_MAGERROR selects the build

Install

Same as v1.0. The downloader db now includes both games automatically. If installing manually, Magical Error needs its own RBF (magerror.rbf in _Arcade/cores/) and the magerror.zip ROM set in games/mame/.

Hyper Duel

The Hyper Duel RBF is unchanged from v1.0 (Hyprduel_20260719.rbf, md5 87b6ee7d). No need to re-download if you already have it.

Verification

Both the magerror SDRAM soak (2200 frames, all integrity counters zero) and the Quartus timing analysis (setup slack +0.285 ns) passed before deploy. On-hardware attract mode confirmed matching MAME.

Assets 7
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Hyper Duel v1.0 (2026-07-19)

Hyper Duel v1.0 (2026-07-19)

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@searchsolved searchsolved released this 19 Jul 14:25
v1.0
4e450b7

First release of the Hyper Duel arcade core for MiSTer - the first RTL implementation of the Imagetek I4220 video chip.

Install

  1. Copy Hyprduel_20260719.rbf to /media/fat/_Arcade/cores/ (rename to Hyprduel.rbf if you prefer, the MRAs reference the dated name pattern via Hyprduel)
  2. Copy Hyper Duel.mra (and optionally Hyper Duel (Set 2).mra) to /media/fat/_Arcade/
  3. Put your hyprduel.zip ROM set (MAME 0.288 naming) in /media/fat/games/mame/

md5 of the RBF: 87b6ee7d275b96c4b01a635fac204335

Highlights

  • CRT-verified against real PCB footage; deviations documented honestly in docs/ACCURACY.md
  • Native 60.24 Hz refresh (measured from two independent PCB recordings; mains-hum spectral evidence in the repo) with a 60 Hz compatibility option
  • Implements the I4220 CRTC display window - the real monitor shows chip lines 2-225, which is why the real board never shows the garbage top lines MAME displays
  • Hiscore autosave (Autosave Hiscores option + OSD-open save, standard MiSTer hiscore flow)
  • Two players, all DIPs, full Verilator parity suite + SDRAM-soak gated builds

Release checks

This bitstream passed, in order: the full Verilator parity suite, the always-on integrity gates over a 2,200-frame SDRAM-model soak with the hardware DIP configuration, a clean Quartus timing summary, an md5-verified deploy, and on-hardware verification on a CRT including a hiscore power-cycle test.

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