v0.1.0

A test runner for FPGA verification work: build the bitstream, keep the old
ones, run the tests on the board, compare against the baseline. Console,
terminal and window interfaces over the same run.

This is a 0.x on purpose. The interfaces are settled and the self tests cover
them, but the tool has only been used on the projects in examples/, and the
first outside project will find things.

Getting it

git clone https://github.com/shchuchkin-pkims/xilinx-test-runner
cd xilinx-test-runner
./bin/xtr --help

Or pip install ., and pip install ".[gui]" for the window. Python 3.11 or
newer needs nothing else; 3.10 pulls in tomli and nothing more.

Where to start

cd examples/demo_project      # runs with no vendor tools installed at all
../../bin/xtr run
../../bin/xtr --gui

examples/pynq_z1 is the same thing on real hardware: a written specification,
RTL, a simulation testbench and tests that run on a Digilent PYNQ-Z1 over the
JTAG cable that programs it.

What is in it

• Five verdicts, so a missing board is not a failure and an open defect does
  not hide under green.
• Build outputs kept as named variants carrying a hash of the sources they came
  from, which a check based on file dates cannot get right.
• One comparison against an accepted baseline instead of one per family of
  tests, over measurements and named checks.
• Execution over ssh, including killing the remote process tree on stop.
• Seeds recorded per run and per test, so random stimulus can be replayed.
• Reports in text, JSON, JUnit XML and HTML, each carrying tool versions,
  source revision, active artifact, machine and seed.
• Console, curses and Qt interfaces over one shared run state.

94 self tests, run on Python 3.10 to 3.13 on every push.

Known limits

• Linux only: the process handling relies on POSIX process groups and file
  locks.
• The window needs PyQt6 or PyQt5; everything else works without Qt.
• Not affiliated with AMD, Cadence, Siemens or Intel. See TRADEMARKS.md.