SRAM synthesis

[ollelogdahl]

Hello,

I'm somewhat new to this field and trying to learn by doing. I really like your tool! I'm currently trying to build something on sky130, and want to use some SRAM. I am early in development, working inside Chisel, so I would like a way to have very dynamic SRAM sizing. My final HDL contains behavioural reg array modules, which I want for synthesis to become SRAM blocks. Is there a way to invoke the OpenRAM compiler for this? I noticed there is no tool for this. Or do people not use OpenRAM?

Sorry if my question is stupid.

Best!

[ollelogdahl]

And also if this was a tool (consider trying to build it) how should it really work? Look for annotations on the verilog blocks, figure out sizes, and automatically generate for the target PDK?

[gadfort]

@ollelogdahl we don't have openram as a tool you can invoke. Depending on what you actually need, you could try openram or there is a new tool inside openroad which is being built to build a memory as well (I would lean towards that solution if it works but at the moment it's still pretty new: https://github.com/gadfort/OpenROAD/tree/master/src/ram).

As for how it should work, there isn't going to be one correct way to do this. You could try to parse the verilog, but I believe chisel might emit a memory file you could use instead (should be much easier). Then you would just need to build a flow / task that can take in the relevant parameters and output a LEF, GDS, liberty model, and verilog model, that should be enough to use them.
Once you have them they can be treated just like any memory we have and create a Library for them that the RTL->GDS flows can use.