Guidance on Integration
Table of Contents:
Tip
If creating a new target board for LOKI, you should refer to the main connector pin guidelines first.
The debug headers are 1.27mm pitch 2x5 headers. 10-pin SWD ribbons should be hardware compatible, and can be broken out to a more common 2.54mm pitch used on most breadboards. Each has pin 1 marked.
| Pin Number | Signal | Purpose | TE0803 Package Pin |
|---|---|---|---|
| 1 | HP_G1_L16_P | 1v8 IO | F2 |
| 2 | HP_G1_L16_N | 1v8 IO | E2 |
| 3 | HP_G1_L17_P | 1v8 IO | |
| 4 | HP_G1_L17_N | 1v8 IO | |
| 5 | HP_G1_L18_P | 1v8 IO | |
| 6 | HP_G1_L18_N | 1v8 IO | |
| 7 | HP_G1_L19_P | 1v8 IO | |
| 8 | HP_G1_L19_N | 1v8 IO | |
| 9 | VDD3V3 | 3.3v output | |
| 10 | GND | Ground |
| Pin Number | Signal | Purpose |
|---|---|---|
| 1 | VDD1V8 | 1.8v output |
| 2 | NRST_ZYNQ | Reset net: pull to ground to reset LOKI |
| 3 | SYSMON_V_P | Sysmon analog input - Positive |
| 4 | SYSMON_V_N | Sysmon analog inpput - Negative |
| 5 | SYSMON_DX_P | Sysmon thermal diode - Positive |
| 6 | SYSMON_DX_N | Sysmon thermal diode - Negative |
| 7 | SCL_DBG1 | Debug header I2C Bus 1 - Clock |
| 8 | SDA_DBG1 | Debug header I2C Bus 1 - Data |
| 9 | VDD3V3 | 3.3v output |
| 10 | GND | Ground |
| Pin Number | Signal | Purpose |
|---|---|---|
| 1 | VDD1V8 | 1.8v output |
| 2 | GND | Ground |
| 3 | DBG_CLKOUT_1_P | Debug Header clock output 1 - ZL30266 OC8 - Positive |
| 4 | DBG_CLKOUT_1_N | Debug Header clock output 1 - ZL30266 OC8 - Negative |
| 5 | DBG_CLKOUT_0_P | Debug Header clock output 0 - ZL30266 OC7 - Positive |
| 6 | DBG_CLKOUT_0_N | Debug Header clock output 0 - ZL30266 OC7 - Negative |
| 7 | SCL_DBG2 | Debug header I2C Bus 2 - Clock |
| 8 | SDA_DBG2 | Debug header I2C Bus 2 - Data |
| 9 | VDD3V3 | 3.3v output |
| 10 | GND | Ground |
| Pin Number | Signal | Purpose | TE0803 Package Pin |
|---|---|---|---|
| 1 | HD_G2_L2_N | 3v3 IO | G10 |
| 2 | HD_G2_L2_P | 3v3 IO | H11 |
| 3 | HD_G2_L3_N | 3v3 IO | H12 |
| 4 | HD_G2_L3_P | 3v3 IO | J12 |
| 5 | HD_G2_L4_N | 3v3 IO | F11 |
| 6 | HD_G2_L4_P | 3v3 IO | F12 |
| 7 | HD_G2_L5_N | 3v3 IO | A10 |
| 8 | HD_G2_L5_P | 3v3 IO | |
| 9 | VDD3V3 | 3.3v output | |
| 10 | GND | Ground |
Warning
Transceivers - only GTH0 on TE0803 4AE11 Modules
The number of available transceivers is limited by the module choice. Our module series of choice is the TE0803 (though the carrier should technically support TE0807 and TE0808 for full transceiver selection), which only has 4 lanes on GTH0. These lanes are also only present on TE0803 modules with Zu4x FPGA SoC variants.
The typical TE0803 4AE11 modules we use have these four lanes only.
LOKI - Main Connector Layout - v3.1 30-07-2025.pdf
LOKI - Main Connector Pins - v3.1 30-07-2025.pdf
Latest versions of these can be found on the Detector Hub Teams if you already have access.