Guidance on Integration

LOKI - Guidance on Integration

Contents

Debug Headers

The debug headers are 1.27mm pitch 2x5 headers. 10-pin SWD ribbons should be hardware compatible, and can be broken out to a more common 2.54mm pitch used on most breadboards. Each has pin 1 marked.

Connector Locations

Pinouts

PL5 - 1.8v IO Header

Pin Number	Signal	Purpose
1	HP_G1_L16_P	1v8 IO
2	HP_G1_L16_N	1v8 IO
3	HP_G1_L17_P	1v8 IO
4	HP_G1_L17_N	1v8 IO
5	HP_G1_L18_P	1v8 IO
6	HP_G1_L18_N	1v8 IO
7	HP_G1_L19_P	1v8 IO
8	HP_G1_L19_N	1v8 IO
9	VDD3V3	3.3v output
10	GND	Ground

PL4 - Zynq Monitor, Reset and I2C

Pin Number	Signal	Purpose
1	VDD1V8	1.8v output
2	NRST_ZYNQ	Reset net: pull to ground to reset LOKI
3	SYSMON_V_P	Sysmon analog input - Positive
4	SYSMON_V_N	Sysmon analog inpput - Negative
5	SYSMON_DX_P	Sysmon thermal diode - Positive
6	SYSMON_DX_N	Sysmon thermal diode - Negative
7	SCL_DBG1	Debug header I2C Bus 1 - Clock
8	SDA_DBG1	Debug header I2C Bus 1 - Data
9	VDD3V3	3.3v output
10	GND	Ground

PL3 - Clock Generator Outputs, I2C

Pin Number	Signal	Purpose
1	VDD1V8	1.8v output
2	GND	Ground
3	DBG_CLKOUT_1_P	Debug Header clock output 1 - ZL30266 OC8 - Positive
4	DBG_CLKOUT_1_N	Debug Header clock output 1 - ZL30266 OC8 - Negative
5	DBG_CLKOUT_0_P	Debug Header clock output 0 - ZL30266 OC7 - Positive
6	DBG_CLKOUT_0_N	Debug Header clock output 0 - ZL30266 OC7 - Negative
7	SCL_DBG2	Debug header I2C Bus 2 - Clock
8	SDA_DBG2	Debug header I2C Bus 2 - Data
9	VDD3V3	3.3v output
10	GND	Ground

PL2 - 3.3v IO Header

Pin Number	Signal	Purpose
1	HD_G2_L2_N	3v3 IO
2	HD_G2_L2_P	3v3 IO
3	HD_G2_L3_N	3v3 IO
4	HD_G2_L3_P	3v3 IO
5	HD_G2_L4_N	3v3 IO
6	HD_G2_L4_P	3v3 IO
7	HD_G2_L5_N	3v3 IO
8	HD_G2_L5_P	3v3 IO
9	VDD3V3	3.3v output
10	GND	Ground

Main Connector Layout and Pins - Detailed Spec

LOKI - Main Connector Layout - v3.1 30-07-2025.pdf

LOKI - Main Connector Pins - v3.1 30-07-2025.pdf

Latest versions of these can be found on the Detector Hub Teams if you already have access.