Skip to content

Releases: stone926/BUAA-CO-Toolkit

v1.2.0

Choose a tag to compare

@github-actions github-actions released this 02 Sep 17:29
  • feat(verilog): bundle Icarus Verilog 13.0 for Linux x64 and ARM64, built and verified on Ubuntu 22.04 with no separate Icarus installation required
  • perf(packaging): include only the matching platform's Icarus runtime in each Windows, macOS, and Linux VSIX while preserving its licenses and corresponding-source information
  • fix(lsp): preserve pending on-save compiler diagnostics when unrelated VS Code settings change
  • test(ci): verify the final VSIX on five native platforms, including real VS Code activation, LSP diagnostics, simulation commands, and a fixed P4 Worker trace comparison; reuse these checks before publishing

v1.1.1

Choose a tag to compare

@github-actions github-actions released this 02 Sep 16:30
  • fix(release): keep corresponding-source filenames stable through GitHub Release upload and verify both SHA256SUMS and the final remote asset-name set

v1.1.0

Choose a tag to compare

@github-actions github-actions released this 01 Sep 05:28
  • feat(verilog): bundle Icarus Verilog 13.0 for macOS 14+ on Apple Silicon and Intel, with no Homebrew installation required; keep ISE/ISim-only features Windows x64-only
  • chore(release): publish and smoke-test win32-x64, darwin-arm64, and darwin-x64 VSIX packages on native runners, and attach deduplicated corresponding sources to the GitHub Release

v1.0.7

Choose a tag to compare

@github-actions github-actions released this 31 Aug 15:41
  • fix(test-cli): align bundled Icarus preflight (2048966)
  • perf(course-testing): cache simulation builds and reduce IO (c9ef1e9)
  • feat(toolchain): prefer bundled assembler and Icarus (9adc6f9)

v1.0.6

Choose a tag to compare

@github-actions github-actions released this 31 Aug 07:44
  • fix(course-testing): surface the first path-safe Icarus/ISim compile or runtime diagnostic in continuous-test reports, bound simulator process output, and preserve private Icarus failure logs with each reproducible case
  • refactor(config): reduce the normal Settings UI from 42 low-level options to 20 course and user-experience settings, while keeping existing advanced values compatible and hidden unless configured
  • fix(config): apply resource and machine scopes consistently, derive project defaults from the selected Profile, and keep machine tool paths out of workspace settings

v1.0.5

Choose a tag to compare

@github-actions github-actions released this 30 Aug 18:25
  • fix(verilog): enable the bundled Windows Icarus processes' UTF-8 code page so projects and temporary files with non-ASCII paths work independently of the system locale
  • test(release): run the packaged-runtime Unicode-path smoke in regular Windows portability CI before a release tag is created

v1.0.2

Choose a tag to compare

@github-actions github-actions released this 13 Aug 12:09
  • fix(course-testing): target stable Mars v0.6.3 (a026eab)

v1.0.1

Choose a tag to compare

@github-actions github-actions released this 12 Aug 14:42
  • refactor(highlighting)!: delegate semantic colors to VS Code (661dc00)
  • feat(highlighting): rebuild syntax and semantic coloring (42c9c8a)
  • fix(verilog): preserve ISE project compilation order (57173f5)
  • docs: 移除冗余审查文档 (0bcc7bc)
  • fix(course-testing): align automatic tests with course semantics (27b73ce)
  • fix(verilog): expand begin completion to block (23f90d6)
  • feat(verilog): filter noisy ISE port warnings (314b4e1)

v1.0.0

Choose a tag to compare

@github-actions github-actions released this 03 Jul 07:45
  • 微调默认指令集 (98aa6c0)
  • 微调默认指令集 (27f6bf8)
  • chore: keep setting descriptions user-facing (a0643f2)
  • 修改p7测试配置默认值 (d3f2c04)
  • 修改p7测试配置默认值 (0c9ec4f)
  • chore: improve generator instruction setting description (c74f3a5)
  • chore: regroup vscode settings (9e5fd5c)
  • 修改p7测试配置默认值 (1604093)
  • refactor: remove Verilog format style preset (ba660d2)
  • fix: remove Verilog alignment legacy fallback (5347a36)
  • fix: group Verilog alignment settings (b027db5)
  • fix: align ternary chains after inline assign branch (97f88f6)
  • feat: configure Verilog ternary alignment (983c30d)
  • feat: align multiline Verilog ternary chains (f036501)
  • fix: make Verilog port alignment idempotent (f966114)
  • fix: align Verilog module port ranges (2a4ac08)
  • chore: prune unused npm scripts (a52d2b4)
  • chore: sync manifest config in workflows (eeb72c8)
  • fix: 修改配置分组的名称 (07121c2)
  • feat: add configurable Verilog formatter alignment (0f378e6)

v0.7.1

Choose a tag to compare

@github-actions github-actions released this 28 Jun 16:25
  • fix: normalize ISim paths across CI platforms (54d548b)