Computer Architecture Lab - ARM Pipeline Processor Implementation

🎯 Project Overview

This repository contains a comprehensive series of laboratory implementations for a complete ARM-style 5-stage pipelined processor. The project demonstrates fundamental and advanced computer architecture concepts through incremental development, from basic pipeline structures to advanced memory hierarchies and optimization techniques.

Each LAB_* directory represents a progressive implementation stage, building upon previous work to create a fully functional processor capable of executing ARM instruction set operations.

🏗️ Architecture Overview

The final processor implements a classic 5-stage pipeline:

• IF (Instruction Fetch): Program counter management and instruction retrieval
• ID (Instruction Decode): Instruction decoding and register file access
• EXE (Execute): ALU operations and address calculations
• MEM (Memory): Data memory access and load/store operations
• WB (Write Back): Result write-back to register file

Advanced features include hazard detection, data forwarding, SRAM integration, and FPGA implementation with debugging capabilities.

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✅ Goals

• Provide a working 5-stage pipelined ARM-like CPU (IF, ID, EXE, MEM, WB).
• Demonstrate pipeline control, forwarding (bypass), hazard detection, memory hierarchy (SRAM + optional cache), and FPGA integration/debugging using VIO/ILA.
• Supply modular testbenches so students can verify individual stages and end-to-end behavior.

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📁 Repository Structure

Laboratory Directories

LAB_1/ to LAB_6/          # Incremental lab implementations
├── README.md             # Comprehensive lab documentation
├── AGENTS.md             # AI assistant instructions
├── CLAUDE.md             # Claude-specific guidelines
├── description/          # Lab specifications and documentation
├── code/                 # Main source code implementation
│   ├── modules/          # Modular Verilog components
│   ├── wrappers/         # FPGA wrappers and top-level modules
│   └── [testbenches]     # Simulation testbenches
├── hw/                   # Hardware-specific files (.xdc, .vhd)
├── docs/                 # Additional documentation and diagrams
├── results/              # Simulation results and analysis
│   ├── logs/             # Simulation log files
│   ├── reports/          # Performance and synthesis reports
│   └── scripts/          # Analysis and measurement scripts
├── report/               # Laboratory report (LaTeX)
└── archive/              # Previous versions and backups

Shared Resources

• archive/ — Legacy projects and shared components
• docs/ — Course documentation and reference materials
• Final_Report/ — Comprehensive project documentation

See per-lab READMEs for lab-specific instructions (LAB_5/README.md is included and contains forwarding & VIO instructions).

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🔍 Key files & modules

• ARM.v — top-level CPU (instantiates stages and pipeline registers).
• IF_stage, ID_stage, EXE_Stage, MEM_Stage, WB_Stage — stage implementations.
• *_stage_reg.v — pipeline registers (IF/ID, ID/EXE, EXE/MEM, MEM/WB).
• Forwarding_Unit.v, Hazard_Detection_Unit — hazard resolution and forwarding control.
• dist_mem_gen_0 / InstructionMemory / *.coe — instruction ROM wrappers.
• LAB_5: sram.v, sram_controller.v — behavioral SRAM model + controller for 64-bit transfers.
• LAB_7: cache_controller.v — 2-way set-associative cache (optional in that lab).

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🧪 Quick start — Simulation

Prerequisites: Icarus Verilog, ModelSim/Questa, or Verilator depending on your preferred simulator.

Icarus Verilog example (fast, functional simulation):

# compile (example for LAB_5 base code)
iverilog -o sim \
  LAB_5/base_code/IF_stage.v \
  LAB_5/base_code/ID_stage.v \
  LAB_5/base_code/EXE_stage.v \
  LAB_5/base_code/MEM_stage.v \
  LAB_5/base_code/WB_stage.v \
  LAB_5/base_code/ARM.v \
  LAB_5/base_code/ARM_TB.v

# run
vvp sim

ModelSim/Questa: use vlog to compile and vsim -c to run the TB with run -all.

Verilator (cycle-accurate C++ harness): use verilator --cc --exe --build then run ./obj_dir/V<top>.

Notes: include sram.v and sram_controller.v when testing memory/cache interactions. If Xilinx IP (dist_mem_gen_0) is missing, use the provided .coe or InstructionMemory wrapper.

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🛠️ Quick start — FPGA (Vivado)

1. Open the lab project in Vivado and add the sources in the chosen LAB_* folder.
2. Create a block design if you want to add IP (ILA/VIO). Add an ila_0 core for debug capture and a vio_0 core if you want runtime control of forwarding.
3. If using VIO, configure it with a single output probe (1-bit) and connect its probe to the wrapper expecting probe_out0 (the wrapper has an ifdef USE_VIO guarded instantiation).
4. Optionally assign a physical button to the forward_en top port in pin_assignment.xdc (LAB_5 maps forward_en -> J15).
5. Synthesize, implement and generate a bitstream, then program the board.
6. Use Hardware Manager to toggle the VIO probe and use ILA captures to compare pipeline behavior with forwarding ON/OFF.

Tip: define USE_VIO for the design when using vio_0 (e.g. add -D USE_VIO in synthesis settings or +define+USE_VIO for simulation flows).

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🔁 Forwarding & VIO (LAB_5) — Summary

• Forwarding enabled (forward_en = 1): ALU RAW hazards are resolved by forwarding; only load-use hazards require a 1-cycle stall.
• Forwarding disabled (forward_en = 0): the Hazard Detection Unit behaves like earlier labs and stalls on any RAW hazard.
• Control of forwarding:
  • VIO: add vio_0 IP with 1 output probe; connect it and define USE_VIO.
  • Button: map forward_en to a board pin (default: J15 in pin_assignment.xdc).
• ILA recommendations: use Number of Windows = 2, capture register file words and PC, then compare captures with forwarding ON vs OFF.

For full step-by-step guidance see LAB_5/README.md (included in this repo).

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🧾 Per-lab highlights

• LAB_1–LAB_3: basic pipeline, register file, hazards, and control.
• LAB_4: Hazard Detection & basic stalling behavior.
• LAB_5: SRAM model + forwarding (VIO/ILA integration).
• LAB_6–LAB_7: incremental additions (performance improvements, cache integration in LAB_7).

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✅ Tests & automation

• scripts/run_tests.sh runs available testbenches using Icarus (ensure Icarus is installed).
• scripts/Makefile contains convenience targets for simulation flows.
• Consider adding your own CI or local scripts to run iverilog and parse results.

If you'd like, I can add an automated testbench that toggles forwarding_enable during a simulation and asserts correct results — tell me and I’ll add it.

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🧭 Coding style & contributions

• Use explicit widths for signals. Avoid implicit sizes.
• Use non-blocking assignments (<=) in sequential always blocks and blocking (=) in combinational always blocks.
• Add module headers describing purpose, I/O, and author.

Please open feature branches and PRs for major changes and include tests that demonstrate behavior changes.

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ℹ️ Known notes & tips

• For debug & validation use the included ila_0 to capture internal registers; add VIO to toggle control signals (forwarding) at runtime.
• If you see mismatches between simulation and FPGA runs, verify IP core wrapper versions (e.g., dist_mem_gen) and timing constraints.

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📬 Support / Contact

• For questions about labs or help running simulations, contact your course TA or the project maintainer listed in the course materials.

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📄 License

This repository is provided for educational use. If you plan to reuse code outside coursework, contact the original authors. For lab exercises, assume an MIT-style permissive approach.

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If you'd like, I can now:

• Add an automated testbench that toggles forwarding and asserts behavior, or
• Add a small Vivado TCL script to automate ILA captures and VIO toggling.

Which would you like me to add next?