3.Different Testing Done on ULX3S Board
Various tests were conducted, particularly on external components, to verify their correct functionality. For the internal digital FPGA block, simulations were performed to ensure proper operation.
To verify the functionality of the LVDS pins, a simple test was implemented. The corresponding Verilog code can be seen here.
In this Verilog code, the signal received at the lvds_p pin, which is declared as an LVDS pin in the constraint file, is processed. The Lattice FPGA is configured to output the LVDS signal on every clock edge, as demonstrated in line 16 of the Verilog code.
By applying an external voltage source to the positive and negative LVDS pins, the behavior of the LVDS output can be verified. When a positive differential voltage of +100mV is applied, the LVDS output is confirmed to be high, resulting in 3.3V. Conversely, when a negative differential voltage of -100mV is applied, the output is low, corresponding to 0V.
After successfully testing the LVDS pins, attention shifted to testing the ADC. Since the design uses a sigma-delta ADC, it underwent a similar validation. Lattice provides an AppNote for implementing a Sigma-Delta ADC design using LVDS pins. The code from this AppNote was utilized in the design, with the only addition being a PWM block. This block uses the digital output of the Sigma-Delta ADC to control the duty cycle. The following results will be shown below.
Figure 1: PWM output when the Analog input is 0V.
As can be seen on Figure 1, when the analog input is 0V the duty cycle is also close to 0%. It isn't a completely straight line on 0V because of the input noise.
Figure 2: PWM output when the Analog input is 1.65V.
On Figure 2 the analog input is half of 3.3V, which corresponds to 1.65V and the duty cycle is 50% accordingly.
Figure 3: PWM output when the Analog input is 3.3V.
While, as the final test the input analog voltage is the highest at 3.3V which shows the PWM output duty cycle close to 100%. And this test validates the working principle of the ADC, where the one bit analog input is oversampled and decimated to give back a _12 bit_signal that feeds the PWM block.
After completing the input testing, the final stage involved evaluating the speaker output. A digital PWM signal generator was implemented in Verilog to test the speakers. Initially, a PWM signal was used to generate a single frequency at a time. Subsequently, a more complex signal, resembling a police siren, was tested, with the frequency increasing and decreasing within the range of human hearing to further assess the speaker's performance. The code for the police siren can be evaluated here.