6. PWM DAC Example

PWM DAC Example

In this example, consider a scenario where a PWM signal with a 100kHz frequency and a 50% duty cycle is utilized. Assuming the signal operates within a voltage range of 0V to 3.3V, the expected Mean Value at the DAC output would be approximately 1.65V. The critical factor in achieving the accurate analog output is the selection of a suitable low-pass filter that effectively converts the PWM signal to its corresponding analog value.

Employing a simple RC first-order low-pass filter, characterized by a one-pole transfer function with a pole located at $\frac{1}{RC}$, and choosing a capacitance value of $C = 10nF$ and a resistance of $R = 318$ $\Omega$, the DAC's output response is illustrated in Figure 1. Additionally, the FFT analysis of the PWM signal prior to filtering is presented in Figure 2, while Figure 3 showcases the FFT results following the filtering process.

Figure 1: DAC Output for 1st order RC filter where R = 318 Ω, C = 10nF.

Figure 2: FFT of PWM signal.

Figure 3: FFT of DAC signal.

Observing Figure 1, it becomes apparent that the DAC's output does not align with the expected outcome, where the role of the RC filter is to eliminate all harmonic components, retaining only the DC part to derive the analog signal. The problem in achieving this stems from the chosen RC values being too low.

The FFT analysis, as visualized, confirms the characteristic spectral pattern of a square wave in the PWM signal. This pattern is marked by a prominent peak at the carrier frequency, followed by diminishing harmonics at odd multiples of the carrier frequency, specifically at three times, five times the carrier frequency, and so on. This spectral composition is largely unaffected by variations in the duty cycle, maintaining a consistent frequency spectrum across different duty cycles.

Figure 4: DAC Output for 1st order RC filter where R = 15,924 Ω, C = 10nF.

Figure 5: FFT of PWM signal.

Figure 6: FFT of DAC signal.

The improvement in ripple is significant on Figure 4, but the prolonged duration required for the output to stabilize at the intended DAC voltage presents a problem. This effect stems from the higher resistance in the RC filter, which, while reducing the cutoff frequency, at the same time extends the time constant. A higher resistance value diminishes the current flow towards the capacitor, resulting in a slower charging rate for the capacitor. Looking at Figure 6, the higher harmonics are properly attenuated and mostly the DC component is present, although a bit reduced at approximately 1.4V. Enhancements to this design could involve adopting a higher-order low-pass filter.