v1.1.1

CPU optimizations: DTC grain cache, -O2, single-precision fixes

- Add DTC pre-fetch cache for grain buffer reads (DRAM→DTC copy before
  each grain block, single-cycle reads instead of random DRAM access)
- Move reverb delay lines to DTC when available (~48KB single-cycle)
- Switch compiler from -Os to -O2 for hardware target
- Replace ReadHermiteStereo with ReadHermiteStereoFast in delay engine
- Add FastPowUnit IEEE754 approximation for delay slicer envelope
- Replace std::pow with exp2/logf in grain duration calculations
- Fix double-precision promotion: logf/expf replacing std::log/std::exp
  in auto_gain, mu-law, random, and delay engine hot paths
- Add adaptive interpolation (linear when grain count > half cap)
- Tighten dynamic grain cap multiplier from 2.0 to 1.5
- Fix uninitialized _NT_sclInfo in parameterString
- Bound pitch quantizer normalization loops to prevent runaway with
  degenerate scales
- Clamp SCL ratios to 1e-9 minimum to prevent log2(-inf/NaN)
- Fix pre-delay counter not decrementing in DTC cached path

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>