Electronic Design Automation | Physical Design | Differentiable Optimization
- I am a Ph.D. student at the School of Integrated Circuits, Southeast University.
- My research focuses on electronic design automation (EDA), physical design, and AI-assisted chip design.
- I am currently exploring differentiable optimization for clock tree synthesis, jointly optimizing topology, timing, and physical objectives.
- I enjoy building research prototypes that connect optimization algorithms with practical chip-design flows.
- Electronic Design Automation
- Physical Design and Clock Tree Synthesis
- Differentiable and Gradient-based Optimization
- Probabilistic Graphical Models for Chip Design
- AI for Integrated Circuits
DCTS is a differentiable clock tree synthesis framework based on a probabilistic graphical model. It formulates discrete topology construction and buffer sizing as a continuous gradient-based optimization problem, jointly considering wire length, fanout, delay, skew, and area before exporting the optimized result as physical-design ECO commands.
| Research challenge | Core approach | Practical output |
|---|---|---|
| Joint clock-tree topology and buffer optimization | Probabilistic graphical modeling with gradient-based optimization | Physical-design ECO commands |
Researching practical, optimization-driven methods for the next generation of chip design automation.