feat(machine/stm32): make HSE crystal frequency selectable.#5517
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Thank you for working on this @digitalentity A few comments: F407 PLL parameters we actually changed. They are probably more correct now, but might want to document this. The STM32WLx boards (nucleowl55jc, lorae5, gnse) also use HSE (HSE32/32 MHz TCXO) but are not covered by this PR. It that intentional? The PR changes CPUFrequency() from a constant return to a computed value. There are no tests verifying this, might be good to add some. |
True. I added code comments to explain this. Re/ The WLx boards - the HSE32 there is a fixed on-package 32MHz TCXO (per RM0461), not a discrete external crystal
I'm not sure that's feasible. We don't have tests for any machine-specific code and |
Define the board's external crystal (HSE) frequency `xtalHz` in the respective `board_*.go` files. Per-topology PLL tables (F1, F4, F7) will compute the register dividers from it. Moving this parameter to the board definition level cleanly isolates board hardware characteristics from general MCU chip configurations, eliminating the need for custom target build tags. Targets using HSE-clocked STM32 chips must define `xtalHz` or fail to build.
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| // PLLParams holds the HSE main-PLL dividers/multipliers (RCC_PLLCFGR M/N/P/Q/R | ||
| // fields) needed to reach a chip's target VCO/SYSCLK frequency from a given | ||
| // crystal frequency. R is left zero on chips without a PLLR output. | ||
| type PLLParams struct { |
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Is this intended to be referenced from outside the package? It seems to be used only internally for now, so I think unexported (pllParams) would be fine.
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The machine.PLLParamsXXXMHz() functions are called from the runtime (e.g. from the src/runtime/runtime_stm32f405.go). So unfortunately this has to be exported unless we want to do massive refactoring and consolidate all clock initialization in either machine or runtime package.
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Thanks for the explanation, that makes sense.
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Thank you for working on this @digitalentity now merging.
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Define the board's external crystal (HSE) frequency
xtalHzin the respectiveboard_*.gofiles. Per-topology PLL tables (F1, F4, F7) will compute the register dividers from it.Moving this parameter to the board definition level cleanly isolates board hardware characteristics from general MCU chip configurations, eliminating the need for custom target build tags. Targets using HSE-clocked STM32 chips must define
xtalHzor fail to build.Fixes #5516