#

aes-wrapper

Here is 1 public repository matching this topic...

HYSUM-TOBBETU / AES-Encryption-Verilog-Pipelined-Implementation-128bit

Device: Zedboard xc7z020clg484-1, Clock Rate: 319 MHz, Tool: Vivado 2018.3, Language: Verilog

fpga matrix verilog vivado mds zedboard xor sbox aes-engine clock-rate aes-wrapper rcon-matrices

Updated Feb 1, 2021
Verilog

Improve this page

Add a description, image, and links to the aes-wrapper topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the aes-wrapper topic, visit your repo's landing page and select "manage topics."