A framework to train a ResUNet architecture, quantize, compile and execute it on an FPGA.

This Repo contains a programs of calling Xilinx Alveo accelerator card from MATLAB

This demo is intended to demonstrate the FPGA design protection and metering capability provided by the Accelize Distribution Platform.

Xilinx DPU(Vitis AI)を用いたエッジAI実現に向けたサンプルプログラム

Web application to transcribe data for the Alveo project

Neural network inferences on Alveo cards with hls4ml framework

PYNQ bindings for C and C++ to avoid requiring Python or Vitis to execute hardware acceleration.

5-point Relative Pose Problem for PYNQ

Business Rule Engine Hardware Accelerator

Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.

Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ

Introductory examples for using PYNQ with Alveo

VNx: Vitis Network Examples

Dataflow QNN inference accelerator examples on FPGAs

Vitis_Accel_Examples

Vitis In-Depth Tutorials