asic
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High-Level Synthesis project for latency optimisation under area constraints
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Jun 7, 2021 - Tcl
Tiny Tapeout 04 Logic IC. Erics submission of his first real microchip doing basic safety chain control
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Jul 30, 2023 - Tcl
Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process
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Dec 31, 2021 - Tcl
Implementation of Timing Exceptions in RTL design for STA
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Sep 15, 2019 - Tcl
A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.
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Jun 14, 2024 - Tcl
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