Implementation of Timing Exceptions in RTL design for STA
-
Updated
Sep 15, 2019 - Tcl
Implementation of Timing Exceptions in RTL design for STA
High-Level Synthesis project for latency optimisation under area constraints
Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process
Tiny Tapeout 04 Logic IC. Erics submission of his first real microchip doing basic safety chain control
A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.
Add a description, image, and links to the asic topic page so that developers can more easily learn about it.
To associate your repository with the asic topic, visit your repo's landing page and select "manage topics."