phoeniX RISC-V Processor

A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding

Verilog implementation of multi-stage 32-bit RISC-V processor

This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum

5-stage pipelined 32-bit MIPS microprocessor in Verilog

KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi

Verilog Snippets for partial fulfilment of CS-F342 Computer Architecture,BITS Pilani

Hardware accelerator for convolutional neural networks

Works of all the labs of Computer Architecture. Contains single-cycle, and pipelined ARM architecture verilog code.

An operating system performs a context switch when it suspends one kernel-level thread and activates a different thread. Typically, data stored in the cache memory are lost in such events. This project aims to explore the advantages of maintaining multiple small "cache-storage-cores" and switching to the appropriate one during a context switch. …

16-bit MIPS processor implemented in Verilog (as a part of Computer Organisation course)

RISC V core implementation using Verilog.

The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pipeline CPU supports the entire RV32IM ISA which contains 45 instructions. The designed pipeline CPU was implemented using behavioral modeling in verilogHDL and icarus Verilog was used compile and simulate. gtkWa…

💻 A 5-stage pipeline MIPS CPU implementation in Verilog.

Dosage is a 20 bit risc cpu, based on Harvard architecrure aimed for educational purposes.

Single-cycle MIPS-like processor with a memory subsystem including a cache.

16 bit CPU created in Vivado with Verilog

5 stages RISC pipelined processor following Harvard architecture.

A simple 5-stage pipelined processor following Harvard's architecture. The processor has RISC-like ISA.

Simulation of the Tomasulo algorithm using python and verilog.Python code has been included to simulate dynamic instruction scheduling.This project was done as the part of Computer Architecture course.