GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.
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Updated
Mar 11, 2024 - C++
GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.
Enables the co-simulation between PSS/E and Matlab/Simulink
GTKWave Decoders for RISCV
Set of utilities to export/import FMUs out of existing C++ code
Integration test between Verilog and C++ using VPI
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