An FPGA implementation of a digital storage oscilloscope.
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Updated
Apr 20, 2017 - VHDL
An FPGA implementation of a digital storage oscilloscope.
Multi-level second-order (Silva Steensgaard Structure) delta-sigma modulator
Expiremental Speech Recognition System using VHDL & MATLAB.
ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)
Floating point FP32 core HDL. For Xilinx FPGAs. Include base converters and some math functions.
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Final project for Hardware Course implemented with VHDL
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