Synchronous and Asynchronous FIFO with AXI interface
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Updated
Nov 20, 2019 - SystemVerilog
Synchronous and Asynchronous FIFO with AXI interface
Repository gathering basic modules for CDC purpose
A systemverilog implementation of the data structures: priority queue, queue and stack
Final project for the class "Application Specific Integrated Circuit Development"
An FPGA implementation of Cummings' Asynchronous FIFO
FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.
Register-based and RAM-based FIFOs designed in Verilog/System Verilog.
This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)
Verilog Codes for various Design
Alchitry Au FPGA Board Example Project
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