Design and implementation of a reconfigurable FIR filter in FPGA
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Updated
Sep 26, 2022 - VHDL
Design and implementation of a reconfigurable FIR filter in FPGA
VHDL description for a circuit which realises a FIR filter with square root raised cosine impulse response
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Modeling, Design and ASIC implementation of a tenth order FIR filter. This project has been developed in two versions: a basic one, and an improved one using 3-level unfolding and five stages pipeline.
Fault tolerant FIR filter designed using N-modular redundancy technique for creating hardware fault tolerance
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