Tool for creating synchronous models and behavioral specifications for asynchronous circuits
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Updated
Jun 19, 2018 - Verilog
Tool for creating synchronous models and behavioral specifications for asynchronous circuits
Verification of Digital Systems (EE382M)
XCrypto: a cryptographic ISE for RISC-V
XCrypto: a cryptographic ISE for RISC-V
Hardware Formal Verification
XCrypto: a cryptographic ISE for RISC-V
SCARV: a side-channel hardened RISC-V platform
PrUcess is a low-power multi-clock configurable digital processing system that executes commands (unsigned arithmetic operations, logical operations, register file read & write operations) which are received from an external source through UART receiver module and it transmits the commands' results through the UART transmitter module.
Formal verification experiments
RTL implementation of a MoldUPD64 receiver.
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
On the TOCTOU Problem in Remote Attestation
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