Pong written with custom ALU in Artix FPGA
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Updated
Dec 15, 2015 - SystemVerilog
Pong written with custom ALU in Artix FPGA
DCF77 Receiver with USB interface in written in SystemVerilog
This is a modified version of the 32-bit MIPS microprocessor. Please refer to "manual.pdf" for more information.
AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emulation Competition 2016.
It's a cryptoprocessor that implements de RC4 algorithm
Reusable image processing modules in SystemVerilog
simple read/write pcap tasks for SystemVerilog test
A sparse matrix multiplication FPGA architecture which acts as a 'coprocessor'.
This repo is for ECE44x (Fall2015-Spring2016)
A Tic-Tac-Toe with multiple level levels and flashing lights implementation using Hardware Definition Language (Verilog) and DE10-Lite Altera Max 10 FPGA.
SHA256 in (System-) Verilog / Open Source FPGA Miner
Stress test power subsystem of your Xilinx FPGA board
SystemVerilog IP-core of highly parametrized Bloom-filter implementation on internal memory
VT220-compatible console on Cyclone IV EP4CE55F23I7
SystemVerilog implementation of the MOS6502
Using Altera FPGA (DE2-115) to finish 3 labs and 1 final project
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