VHDL / System Verilog to Verilog converter, based on Yosys and the plugins ghdl-yosys-plugin and synlig.
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Updated
Feb 4, 2024 - Python
VHDL / System Verilog to Verilog converter, based on Yosys and the plugins ghdl-yosys-plugin and synlig.
A possible replacement for openflow, which would be ideally contributed to the SymbiFlow project
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