This repository contains source code for past labs and projects involving FPGA and Verilog based designs

This repository contains Verilog HDL implementations of Half Adders, Full Adders, and 4-bit Adders, designed at three different abstraction levels: Gate Level, Dataflow Level, and Behavioral Level. These designs are fundamental to digital electronics, and this project showcases the versatility of Verilog in modeling and simulating digital circuits.

Digital System Design Lab Codes using Verilog

A repository for some modules I made while learning Verilog

CSE-2112 Digital Syatem Design LAb

A compact Verilog project implementing a half-adder with gate-level modeling, featuring a detailed testbench for functional verification and simulation.